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https://github.com/AsahiLinux/u-boot
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174 lines
5.2 KiB
C
174 lines
5.2 KiB
C
/*
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* IXP PCI Init
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* (C) Copyright 2004 eslab.whut.edu.cn
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* Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _IXP425PCI_H
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#define _IXP425PCI_H
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#define OK 0
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#define ERROR -1
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struct pci_controller;
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extern void pci_ixp_init(struct pci_controller *hose);
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/* Mask definitions*/
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#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
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#define PCI_NP_CBE_BESL (4)
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#define PCI_NP_AD_FUNCSL (8)
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/*Register addressing definitions for PCI controller configuration
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and status registers*/
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#define PCI_CSR_BASE (0xC0000000)
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/*
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#define PCI_NP_AD_OFFSET (0x00)
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#define PCI_NP_CBE_OFFSET (0x04)
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#define PCI_NP_WDATA_OFFSET (0x08)
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#define PCI_NP_RDATA_OFFSET (0x0C)
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#define PCI_CRP_OFFSET (0x10)
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#define PCI_CRP_WDATA_OFFSET (0x14)
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#define PCI_CRP_RDATA_OFFSET (0x18)
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#define PCI_CSR_OFFSET (0x1C)
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#define PCI_ISR_OFFSET (0x20)
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#define PCI_INTEN_OFFSET (0x24)
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#define PCI_DMACTRL_OFFSET (0x28)
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#define PCI_AHBMEMBASE_OFFSET (0x2C)
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#define PCI_AHBIOBASE_OFFSET (0x30)
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#define PCI_PCIMEMBASE_OFFSET (0x34)
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#define PCI_AHBDOORBELL_OFFSET (0x38)
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#define PCI_PCIDOORBELL_OFFSET (0x3C)
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#define PCI_ATPDMA0_AHBADDR (0x40)
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#define PCI_ATPDMA0_PCIADDR (0x44)
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#define PCI_ATPDMA0_LENADDR (0x48)
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#define PCI_ATPDMA1_AHBADDR (0x4C)
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#define PCI_ATPDMA1_PCIADDR (0x50)
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#define PCI_ATPDMA1_LENADDR (0x54)
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#define PCI_PTADMA0_AHBADDR (0x58)
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#define PCI_PTADMA0_PCIADDR (0x5C)
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#define PCI_PTADMA0_LENADDR (0x60)
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#define PCI_PTADMA1_AHBADDR (0x64)
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#define PCI_PTADMA1_PCIADDR (0x68)
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#define PCI_PTADMA1_LENADDR (0x6C)
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*/
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/*Non prefetch registers bit definitions*/
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/*
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#define NP_CMD_INTACK (0x0)
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#define NP_CMD_SPECIAL (0x1)
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#define NP_CMD_IOREAD (0x2)
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#define NP_CMD_IOWRITE (0x3)
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#define NP_CMD_MEMREAD (0x6)
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#define NP_CMD_MEMWRITE (0x7)
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#define NP_CMD_CONFIGREAD (0xa)
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#define NP_CMD_CONFIGWRITE (0xb)
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*/
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/*Configuration Port register bit definitions*/
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#define PCI_CRP_WRITE BIT(16)
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/*ISR (Interrupt status) Register bit definitions*/
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#define PCI_ISR_PSE BIT(0)
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#define PCI_ISR_PFE BIT(1)
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#define PCI_ISR_PPE BIT(2)
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#define PCI_ISR_AHBE BIT(3)
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#define PCI_ISR_APDC BIT(4)
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#define PCI_ISR_PADC BIT(5)
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#define PCI_ISR_ADB BIT(6)
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#define PCI_ISR_PDB BIT(7)
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/*INTEN (Interrupt Enable) Register bit definitions*/
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#define PCI_INTEN_PSE BIT(0)
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#define PCI_INTEN_PFE BIT(1)
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#define PCI_INTEN_PPE BIT(2)
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#define PCI_INTEN_AHBE BIT(3)
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#define PCI_INTEN_APDC BIT(4)
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#define PCI_INTEN_PADC BIT(5)
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#define PCI_INTEN_ADB BIT(6)
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#define PCI_INTEN_PDB BIT(7)
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/*PCI configuration regs.*/
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#define PCI_CFG_VENDOR_ID 0x00
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#define PCI_CFG_DEVICE_ID 0x02
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#define PCI_CFG_COMMAND 0x04
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#define PCI_CFG_STATUS 0x06
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#define PCI_CFG_REVISION 0x08
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#define PCI_CFG_PROGRAMMING_IF 0x09
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#define PCI_CFG_SUBCLASS 0x0a
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#define PCI_CFG_CLASS 0x0b
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#define PCI_CFG_CACHE_LINE_SIZE 0x0c
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#define PCI_CFG_LATENCY_TIMER 0x0d
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#define PCI_CFG_HEADER_TYPE 0x0e
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#define PCI_CFG_BIST 0x0f
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#define PCI_CFG_BASE_ADDRESS_0 0x10
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#define PCI_CFG_BASE_ADDRESS_1 0x14
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#define PCI_CFG_BASE_ADDRESS_2 0x18
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#define PCI_CFG_BASE_ADDRESS_3 0x1c
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#define PCI_CFG_BASE_ADDRESS_4 0x20
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#define PCI_CFG_BASE_ADDRESS_5 0x24
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#define PCI_CFG_CIS 0x28
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#define PCI_CFG_SUB_VENDOR_ID 0x2c
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#define PCI_CFG_SUB_SYSTEM_ID 0x2e
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#define PCI_CFG_EXPANSION_ROM 0x30
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#define PCI_CFG_RESERVED_0 0x34
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#define PCI_CFG_RESERVED_1 0x38
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#define PCI_CFG_DEV_INT_LINE 0x3c
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#define PCI_CFG_DEV_INT_PIN 0x3d
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#define PCI_CFG_MIN_GRANT 0x3e
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#define PCI_CFG_MAX_LATENCY 0x3f
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#define PCI_CFG_SPECIAL_USE 0x41
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#define PCI_CFG_MODE 0x43
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#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
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#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
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#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
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#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
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#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
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#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
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#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
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#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
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#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
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#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
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/*CSR Register bit definitions*/
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#define PCI_CSR_HOST BIT(0)
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#define PCI_CSR_ARBEN BIT(1)
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#define PCI_CSR_ADS BIT(2)
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#define PCI_CSR_PDS BIT(3)
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#define PCI_CSR_ABE BIT(4)
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#define PCI_CSR_DBT BIT(5)
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#define PCI_CSR_ASE BIT(8)
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#define PCI_CSR_IC BIT(15)
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/*Configuration command bit definitions*/
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#define PCI_CFG_CMD_IOAE BIT(0)
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#define PCI_CFG_CMD_MAE BIT(1)
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#define PCI_CFG_CMD_BME BIT(2)
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#define PCI_CFG_CMD_MWIE BIT(4)
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#define PCI_CFG_CMD_SER BIT(8)
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#define PCI_CFG_CMD_FBBE BIT(9)
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#define PCI_CFG_CMD_MDPE BIT(24)
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#define PCI_CFG_CMD_STA BIT(27)
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#define PCI_CFG_CMD_RTA BIT(28)
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#define PCI_CFG_CMD_RMA BIT(29)
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#define PCI_CFG_CMD_SSE BIT(30)
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#define PCI_CFG_CMD_DPE BIT(31)
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/*DMACTRL DMA Control and status Register*/
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#define PCI_DMACTRL_APDCEN BIT(0)
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#define PCI_DMACTRL_APDC0 BIT(4)
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#define PCI_DMACTRL_APDE0 BIT(5)
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#define PCI_DMACTRL_APDC1 BIT(6)
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#define PCI_DMACTRL_APDE1 BIT(7)
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#define PCI_DMACTRL_PADCEN BIT(8)
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#define PCI_DMACTRL_PADC0 BIT(12)
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#define PCI_DMACTRL_PADE0 BIT(13)
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#define PCI_DMACTRL_PADC1 BIT(14)
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#define PCI_DMACTRL_PADE1 BIT(15)
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#endif
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