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https://github.com/AsahiLinux/u-boot
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4b044082c1
Add set parent support for clk mux Signed-off-by: Peng Fan <peng.fan@nxp.com>
240 lines
5.3 KiB
C
240 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* Simple multiplexer clock implementation
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*/
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/*
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* U-Boot CCF porting node:
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*
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* The Linux kernel - as of tag: 5.0-rc3 is using also the imx_clk_fixup_mux()
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* version of CCF mux. It is used on e.g. imx6q to provide fixes (like
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* imx_cscmr1_fixup) for broken HW.
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*
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* At least for IMX6Q (but NOT IMX6QP) it is important when we set the parent
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* clock.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <linux/clk-provider.h>
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#include <clk.h>
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#include "clk.h"
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#define UBOOT_DM_CLK_CCF_MUX "ccf_clk_mux"
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int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
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unsigned int val)
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{
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struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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int num_parents = mux->num_parents;
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if (table) {
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int i;
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for (i = 0; i < num_parents; i++)
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if (table[i] == val)
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return i;
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return -EINVAL;
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}
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if (val && (flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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if (val && (flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
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{
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unsigned int val = index;
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if (table) {
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val = table[index];
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} else {
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if (flags & CLK_MUX_INDEX_BIT)
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val = 1 << index;
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if (flags & CLK_MUX_INDEX_ONE)
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val++;
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}
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return val;
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}
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u8 clk_mux_get_parent(struct clk *clk)
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{
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struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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u32 val;
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#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
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val = mux->io_mux_val;
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#else
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val = readl(mux->reg);
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#endif
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val >>= mux->shift;
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val &= mux->mask;
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return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
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}
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static int clk_fetch_parent_index(struct clk *clk,
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struct clk *parent)
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{
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struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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int i;
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if (!parent)
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return -EINVAL;
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for (i = 0; i < mux->num_parents; i++) {
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if (!strcmp(parent->dev->name, mux->parent_names[i]))
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return i;
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}
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return -EINVAL;
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}
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static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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int index;
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u32 val;
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u32 reg;
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index = clk_fetch_parent_index(clk, parent);
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if (index < 0) {
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printf("Could not fetch index\n");
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return index;
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}
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val = clk_mux_index_to_val(mux->table, mux->flags, index);
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if (mux->flags & CLK_MUX_HIWORD_MASK) {
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reg = mux->mask << (mux->shift + 16);
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} else {
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reg = readl(mux->reg);
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reg &= ~(mux->mask << mux->shift);
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}
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val = val << mux->shift;
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reg |= val;
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writel(reg, mux->reg);
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return 0;
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}
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const struct clk_ops clk_mux_ops = {
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.get_rate = clk_generic_get_rate,
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.set_parent = clk_mux_set_parent,
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};
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struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table)
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{
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struct clk_mux *mux;
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struct clk *clk;
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u8 width = 0;
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int ret;
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if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
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width = fls(mask) - ffs(mask) + 1;
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if (width + shift > 16) {
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pr_err("mux value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the mux */
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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/* U-boot specific assignments */
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mux->parent_names = parent_names;
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mux->num_parents = num_parents;
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/* struct clk_mux assignments */
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mux->reg = reg;
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mux->shift = shift;
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mux->mask = mask;
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mux->flags = clk_mux_flags;
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mux->table = table;
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#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
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mux->io_mux_val = *(u32 *)reg;
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#endif
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clk = &mux->clk;
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/*
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* Read the current mux setup - so we assign correct parent.
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*
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* Changing parent would require changing internals of udevice struct
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* for the corresponding clock (to do that define .set_parent() method.
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*/
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ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
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parent_names[clk_mux_get_parent(clk)]);
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if (ret) {
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kfree(mux);
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return ERR_PTR(ret);
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}
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return clk;
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}
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struct clk *clk_register_mux_table(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table)
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{
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struct clk *clk;
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clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags,
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table);
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if (IS_ERR(clk))
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return ERR_CAST(clk);
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return clk;
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}
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags)
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{
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u32 mask = BIT(width) - 1;
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return clk_register_mux_table(dev, name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags,
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NULL);
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}
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U_BOOT_DRIVER(ccf_clk_mux) = {
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.name = UBOOT_DM_CLK_CCF_MUX,
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.id = UCLASS_CLK,
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.ops = &clk_mux_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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