mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 19:10:13 +00:00
fe69b030de
Signed-off-by: Peng Fan <peng.fan@nxp.com>
243 lines
6 KiB
C
243 lines
6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <dm/lists.h>
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#include <dm/device-internal.h>
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#include <linux/clk-provider.h>
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#include <linux/log2.h>
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#include <div64.h>
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#include <clk.h>
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#include "clk.h"
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#define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
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static unsigned int _get_table_div(const struct clk_div_table *table,
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unsigned int val)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->val == val)
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return clkt->div;
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return 0;
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}
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static unsigned int _get_div(const struct clk_div_table *table,
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unsigned int val, unsigned long flags, u8 width)
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{
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if (flags & CLK_DIVIDER_ONE_BASED)
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return val;
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << val;
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if (flags & CLK_DIVIDER_MAX_AT_ZERO)
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return val ? val : clk_div_mask(width) + 1;
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if (table)
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return _get_table_div(table, val);
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return val + 1;
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}
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unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
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unsigned int val,
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const struct clk_div_table *table,
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unsigned long flags, unsigned long width)
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{
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unsigned int div;
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div = _get_div(table, val, flags, width);
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if (!div) {
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WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
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"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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clk_hw_get_name(hw));
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return parent_rate;
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}
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return DIV_ROUND_UP_ULL((u64)parent_rate, div);
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}
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static ulong clk_divider_recalc_rate(struct clk *clk)
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{
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struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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unsigned int val;
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#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
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val = divider->io_divider_val;
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#else
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val = readl(divider->reg);
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#endif
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val >>= divider->shift;
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val &= clk_div_mask(divider->width);
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return divider_recalc_rate(clk, parent_rate, val, divider->table,
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divider->flags, divider->width);
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}
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static bool _is_valid_table_div(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return true;
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return false;
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}
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static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
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unsigned long flags)
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{
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return is_power_of_2(div);
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if (table)
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return _is_valid_table_div(table, div);
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return true;
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}
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static unsigned int _get_table_val(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return clkt->val;
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return 0;
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}
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static unsigned int _get_val(const struct clk_div_table *table,
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unsigned int div, unsigned long flags, u8 width)
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{
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if (flags & CLK_DIVIDER_ONE_BASED)
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return div;
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return __ffs(div);
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if (flags & CLK_DIVIDER_MAX_AT_ZERO)
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return (div == clk_div_mask(width) + 1) ? 0 : div;
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if (table)
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return _get_table_val(table, div);
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return div - 1;
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}
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int divider_get_val(unsigned long rate, unsigned long parent_rate,
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const struct clk_div_table *table, u8 width,
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unsigned long flags)
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{
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unsigned int div, value;
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div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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if (!_is_valid_div(table, div, flags))
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return -EINVAL;
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value = _get_val(table, div, flags, width);
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return min_t(unsigned int, value, clk_div_mask(width));
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}
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static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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int value;
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u32 val;
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value = divider_get_val(rate, parent_rate, divider->table,
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divider->width, divider->flags);
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if (value < 0)
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return value;
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = clk_div_mask(divider->width) << (divider->shift + 16);
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} else {
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val = readl(divider->reg);
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val &= ~(clk_div_mask(divider->width) << divider->shift);
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}
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val |= (u32)value << divider->shift;
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writel(val, divider->reg);
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return clk_get_rate(clk);
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}
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const struct clk_ops clk_divider_ops = {
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.get_rate = clk_divider_recalc_rate,
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.set_rate = clk_divider_set_rate,
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};
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static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table)
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{
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struct clk_divider *div;
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struct clk *clk;
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int ret;
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if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
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if (width + shift > 16) {
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pr_warn("divider value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the divider */
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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/* struct clk_divider assignments */
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div->reg = reg;
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->table = table;
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#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
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div->io_divider_val = *(u32 *)reg;
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#endif
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/* register the clock */
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clk = &div->clk;
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ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
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if (ret) {
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kfree(div);
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return ERR_PTR(ret);
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}
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return clk;
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}
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struct clk *clk_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags)
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{
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struct clk *clk;
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clk = _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, NULL);
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if (IS_ERR(clk))
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return ERR_CAST(clk);
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return clk;
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}
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U_BOOT_DRIVER(ccf_clk_divider) = {
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.name = UBOOT_DM_CLK_CCF_DIVIDER,
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.id = UCLASS_CLK,
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.ops = &clk_divider_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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