mirror of
https://github.com/AsahiLinux/u-boot
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b375219e73
The latest Linux can directly handle SMP operations for UniPhier SoCs
without any help of U-boot. Drop the relevant code from U-boot.
See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier:
rework SMP operations to use trampoline code") in Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
122 lines
3.1 KiB
ArmAsm
122 lines
3.1 KiB
ArmAsm
/*
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* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <linux/sizes.h>
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#include <asm/system.h>
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#include <mach/arm-mpcore.h>
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#include <mach/sbc-regs.h>
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#include <mach/ssc-regs.h>
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ENTRY(lowlevel_init)
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mov r8, lr @ persevere link reg across call
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/*
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* The UniPhier Boot ROM loads SPL code to the L2 cache.
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* But CPUs can only do instruction fetch now because start.S has
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* cleared C and M bits.
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* First we need to turn on MMU and Dcache again to get back
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* data access to L2.
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*/
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
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mcr p15, 0, r0, c1, c0, 0
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#ifdef CONFIG_DEBUG_LL
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bl debug_ll_init
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#endif
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/*
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* Now we are using the page table embedded in the Boot ROM.
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* It is not handy since it is not a straight mapped table for sLD3.
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* What we need to do next is to switch over to the page table in SPL.
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*/
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ldr r3, =init_page_table @ page table must be 16KB aligned
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/* Disable MMU and Dcache before switching Page Table */
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
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mcr p15, 0, r0, c1, c0, 0
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bl enable_mmu
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bl setup_init_ram @ RAM area for temporary stack pointer
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mov lr, r8 @ restore link
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mov pc, lr @ back to my caller
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ENDPROC(lowlevel_init)
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ENTRY(enable_mmu)
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mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
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bic r0, r0, #0x37
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orr r0, r0, #0x20 @ disable TTBR1
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mcr p15, 0, r0, c2, c0, 2
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orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
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mcr p15, 0, r0, c2, c0, 0 @ TTBR0
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mov r0, #-1 @ manager for all domains (No permission check)
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mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
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dsb
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isb
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/*
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* MMU on:
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* TLBs was already invalidated in "../start.S"
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* So, we don't need to invalidate it here.
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*/
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr
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ENDPROC(enable_mmu)
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/*
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* For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
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* It is large enough for tmp RAM.
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*/
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#define BOOT_RAM_SIZE (SZ_32K)
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#define BOOT_WAY_BITS (0x00000100) /* way 8 */
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ENTRY(setup_init_ram)
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/*
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* Touch to zero for the boot way
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*/
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0:
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/*
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* set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
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*/
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ldr r0, = 0x00408006 @ touch to zero with address range
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ldr r1, = SSCOQM
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str r0, [r1]
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ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address
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ldr r1, = SSCOQAD
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str r0, [r1]
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ldr r0, = BOOT_RAM_SIZE
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ldr r1, = SSCOQSZ
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str r0, [r1]
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ldr r0, = BOOT_WAY_BITS
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ldr r1, = SSCOQWN
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str r0, [r1]
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ldr r1, = SSCOPPQSEF
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ldr r0, [r1]
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cmp r0, #0 @ check if the command is successfully set
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bne 0b @ try again if an error occurs
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ldr r1, = SSCOLPQS
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1:
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ldr r0, [r1]
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cmp r0, #0x4
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bne 1b @ wait until the operation is completed
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str r0, [r1] @ clear the complete notification flag
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mov pc, lr
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ENDPROC(setup_init_ram)
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