mirror of
https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
149 lines
3.3 KiB
C
149 lines
3.3 KiB
C
/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <asm/arch/ixp425.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include "actux3_hw.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* CS1: IPAC-X */
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writel(0x94d10013, IXP425_EXP_CS1);
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/* CS5: Debug port */
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writel(0x9d520003, IXP425_EXP_CS5);
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/* CS6: Release/Option register */
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writel(0x81860001, IXP425_EXP_CS6);
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/* CS7: LEDs */
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writel(0x80900003, IXP425_EXP_CS7);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
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/*
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* Setup GPIO's for Interrupt inputs
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*/
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
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/*
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* Setup GPIO's for 33MHz clock output
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*/
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
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writel(0x011001FF, IXP425_GPIO_GPCLKR);
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/* we need a minimum PCI reset pulse width after enabling the clock */
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udelay(533);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
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ACTUX3_LED1_RT(1);
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ACTUX3_LED1_GN(0);
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ACTUX3_LED2_RT(0);
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ACTUX3_LED2_GN(0);
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ACTUX3_LED3_RT(0);
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ACTUX3_LED3_GN(0);
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ACTUX3_LED4_GN(0);
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ACTUX3_LED5_RT(0);
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return 0;
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}
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/*
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* Check Board Identity
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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puts("Board: AcTux-3 rev.");
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putc(ACTUX3_BOARDREL + 'A' - 1);
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if (i > 0) {
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puts (", serial# ");
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puts (buf);
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}
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putc('\n');
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return 0;
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}
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/*************************************************************************
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* get_board_rev() - setup to pass kernel board revision information
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* 0 = reserved
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* 1 = Rev. A
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* 2 = Rev. B
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*************************************************************************/
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u32 get_board_rev(void)
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{
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return ACTUX3_BOARDREL;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
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return 0;
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}
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void reset_phy(void)
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{
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int i;
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/* initialize the PHY */
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miiphy_reset("NPE0", CONFIG_PHY_ADDR);
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/* all LED outputs = Link/Act */
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miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
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/*
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* The Marvell 88E6060 switch comes up with all ports disabled.
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* set all ethernet switch ports to forwarding state
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*/
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for (i = 1; i <= 5; i++)
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miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
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}
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