mirror of
https://github.com/AsahiLinux/u-boot
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2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
157 lines
3.1 KiB
C
157 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* board/renesas/porter/porter.c
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Cogent Embedded, Inc.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <cpu_func.h>
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#include <env.h>
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#include <hang.h>
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#include <init.h>
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#include <malloc.h>
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#include <dm.h>
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#include <asm/global_data.h>
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#include <dm/platform_data/serial_sh.h>
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#include <env_internal.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <div64.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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u32 stc;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* CPU frequency setting. Set to 1.5GHz */
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stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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/* QoS */
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qos_init();
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}
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#define TMU0_MSTP125 BIT(25)
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#define SD2CKCR 0xE615026C
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#define SD_97500KHZ 0x7
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int board_early_init_f(void)
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{
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/*
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* SD0 clock is set to 97.5MHz by default.
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* Set SD2 to the 97.5MHz as well.
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*/
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writel(SD_97500KHZ, SD2CKCR);
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return 0;
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}
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#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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/* Force ethernet PHY out of reset */
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gpio_request(ETHERNET_PHY_RESET, "phy_reset");
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gpio_direction_output(ETHERNET_PHY_RESET, 0);
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mdelay(10);
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gpio_direction_output(ETHERNET_PHY_RESET, 1);
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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/* porter has KSZ8041RNLI */
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#define PHY_CONTROL1 0x1E
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#define PHY_LED_MODE 0xC000
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#define PHY_LED_MODE_ACK 0x4000
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int board_phy_config(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
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ret &= ~PHY_LED_MODE;
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ret |= PHY_LED_MODE_ACK;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
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return 0;
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}
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void reset_cpu(void)
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{
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struct udevice *dev;
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const u8 pmic_bus = 6;
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const u8 pmic_addr = 0x5a;
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u8 data;
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int ret;
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ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
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if (ret)
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hang();
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ret = dm_i2c_read(dev, 0x13, &data, 1);
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if (ret)
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hang();
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data |= BIT(1);
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ret = dm_i2c_write(dev, 0x13, &data, 1);
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if (ret)
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hang();
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}
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enum env_location env_get_location(enum env_operation op, int prio)
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{
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const u32 load_magic = 0xb33fc0de;
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/* Block environment access if loaded using JTAG */
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if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
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(op != ENVOP_INIT))
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return ENVL_UNKNOWN;
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if (prio)
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return ENVL_UNKNOWN;
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return ENVL_SPI_FLASH;
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}
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