mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
989091acb0
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
625 lines
18 KiB
C
625 lines
18 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_QE 1 /* Has QE */
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#define CONFIG_MPC83xx 1 /* MPC83xx family */
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#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
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#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
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#define CONFIG_SYS_TEXT_BASE 0xFE000000
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/*
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* System Clock Setup
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*/
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#ifdef CONFIG_PCISLAVE
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#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
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#else
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#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
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#endif
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 66000000
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#endif
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/*
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* Hardware Reset Configuration Word
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*/
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_VCO_1X2 |\
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HRCWL_CSB_TO_CLKIN_2X1 |\
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HRCWL_CORE_TO_CSB_2X1 |\
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HRCWL_CE_PLL_VCO_DIV_2 |\
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HRCWL_CE_PLL_DIV_1X1 |\
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HRCWL_CE_TO_PLL_1X3)
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#ifdef CONFIG_PCISLAVE
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_AGENT |\
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HRCWH_PCI1_ARBITER_DISABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0XFFF00100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LALE_NORMAL)
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#else
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LALE_NORMAL)
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#endif
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/*
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* System IO Config
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*/
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#define CONFIG_SYS_SICRL 0x00000000
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CONFIG_BOARD_EARLY_INIT_R
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/*
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* IMMR new address
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*/
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#define CONFIG_SYS_IMMR 0xE0000000
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
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#undef CONFIG_SPD_EEPROM
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#if defined(CONFIG_SPD_EEPROM)
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/* Determine DDR configuration from I2C interface
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*/
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
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#else
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/* Manually set up DDR parameters
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*/
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#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102
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#define CONFIG_SYS_DDR_TIMING_0 0x00220802
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#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
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#define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
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#define CONFIG_SYS_DDR_MODE 0x44400232
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#define CONFIG_SYS_DDR_MODE2 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL 0x03200064
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#endif
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/*
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* Memory test
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*/
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00100000
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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| (2 << BR_PS_SHIFT) /* 16 bit port */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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/*
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* BCSR on the Local Bus
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*/
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#define CONFIG_SYS_BCSR 0xF8000000
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/* Access window base at BCSR base */
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
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/* Access window size 32K */
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
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/* Port size=8bit, MSEL=GPCM */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
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#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
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/*
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* SDRAM on the Local Bus
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*/
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#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
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#ifdef CONFIG_SYS_LB_SDRAM
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
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#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
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/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
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/*
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* Base Register 2 and Option Register 2 configure SDRAM.
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* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
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*
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* For BR2, need:
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* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
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* port size = 32-bits = BR2[19:20] = 11
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* no parity checking = BR2[21:22] = 00
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* SDRAM for MSEL = BR2[24:26] = 011
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* Valid = BR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
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*
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* CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
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* the top 17 bits of BR2.
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*/
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#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
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/*
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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*
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* For OR2, need:
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* 64MB mask for AM, OR2[0:7] = 1111 1100
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* XAM, OR2[17:18] = 11
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* 9 columns OR2[19-21] = 010
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* 13 rows OR2[23-25] = 100
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* EAD set for extra time OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
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*/
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#define CONFIG_SYS_OR2_PRELIM 0xfc006901
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/* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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/* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
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#endif
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/*
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* Windows to access PIB via local bus
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*/
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/* windows base 0xf8008000 */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
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/* windows size 64KB */
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f
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/*
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* CS2 on Local Bus, to PIB
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*/
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/* CS2 base address at 0xf8008000 */
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#define CONFIG_SYS_BR2_PRELIM 0xf8008801
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/* size 32KB, port size 8bit, GPCM */
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#define CONFIG_SYS_OR2_PRELIM 0xffffe9f7
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/*
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* CS3 on Local Bus, to PIB
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*/
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/* CS3 base address at 0xf8010000 */
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#define CONFIG_SYS_BR3_PRELIM 0xf8010801
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/* size 32KB, port size 8bit, GPCM */
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#define CONFIG_SYS_OR3_PRELIM 0xffffe9f7
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_FSL_I2C
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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/*
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* Config on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
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#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_83XX_PCI_STREAMING
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#undef CONFIG_EEPRO100
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_UEC_ETH
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#define CONFIG_ETHPRIME "UEC0"
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#define CONFIG_UEC_ETH1 /* ETH3 */
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#ifdef CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR 3
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
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#endif
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#define CONFIG_UEC_ETH2 /* ETH4 */
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#ifdef CONFIG_UEC_ETH2
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#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
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#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
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#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 4
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
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#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
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#endif
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/*
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* Environment
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_ASKENV
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CONFIG_SYS_RAMBOOT)
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#undef CONFIG_CMD_SAVEENV
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#undef CONFIG_CMD_LOADS
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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/*
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* Core HID Setup
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*/
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE)
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#define CONFIG_SYS_HID2 HID2_HBE
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/*
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* MMU Setup
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*/
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR: cache cacheable */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
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| BATU_BL_4M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* BCSR: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
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| BATU_BL_128K \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
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| BATU_BL_32M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#define CONFIG_SYS_IBAT4L (0)
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#define CONFIG_SYS_IBAT4U (0)
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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/* Stack in dcache: cacheable, no memory coherence */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
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| BATU_BL_128K \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#ifdef CONFIG_PCI
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/* PCI MEM space: cacheable */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* PCI MMIO space: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#else
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#define CONFIG_SYS_IBAT6L (0)
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#define CONFIG_SYS_IBAT6U (0)
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/ #define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_UEC_ETH)
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
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#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=1000000\0" \
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"ramdiskfile=ramfs.83xx\0" \
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"fdtaddr=780000\0" \
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"fdtfile=mpc832x_mds.dtb\0" \
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""
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
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"$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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#endif /* __CONFIG_H */
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