mirror of
https://github.com/AsahiLinux/u-boot
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274 lines
5.4 KiB
ArmAsm
274 lines
5.4 KiB
ArmAsm
/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2007 Kenati Technologies, Inc.
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*
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* board/sh7763rdp/lowlevel_init.S
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
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write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
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write32 WDTBST_A, WDTBST_D /*
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* 0xFFCC0008
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* Watchdog Base Stop Time Register
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*/
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write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
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/* Instruction Cache Invalidate */
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write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
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/* TI == TLB Invalidate bit */
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write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
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write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
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write32 RAMCR_A, RAMCR_D
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mov.l MMSELR_A, r1
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mov.l MMSELR_D, r0
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synco
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mov.l r0, @r1
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mov.l @r1, r2 /* execute two reads after setting MMSELR */
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mov.l @r1, r2
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synco
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/* issue memory read */
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mov.l DDRSD_START_A, r1 /* memory address to read*/
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mov.l @r1, r0
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synco
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write32 MIM8_A, MIM8_D
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write32 MIMC_A, MIMC_D1
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write32 STRC_A, STRC_D
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write32 SDR4_A, SDR4_D
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write32 MIMC_A, MIMC_D2
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nop
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nop
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nop
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write32 SCR4_A, SCR4_D3
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write32 SCR4_A, SCR4_D2
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write32 SDMR02000_A, SDMR02000_D
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write32 SDMR00B08_A, SDMR00B08_D
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write32 SCR4_A, SCR4_D2
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write32 SCR4_A, SCR4_D4
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nop
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nop
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nop
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nop
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write32 SCR4_A, SCR4_D4
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nop
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nop
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nop
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nop
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write32 SDMR00308_A, SDMR00308_D
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write32 MIMC_A, MIMC_D3
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mov.l SCR4_A, r1
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mov.l SCR4_D1, r0
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mov.l DELAY60_D, r3
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delay_loop_60:
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mov.l r0, @r1
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dt r3
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bf delay_loop_60
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nop
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write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
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bsc_init:
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write32 BCR_A, BCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS1BCR_A, CS1BCR_D
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write32 CS2BCR_A, CS2BCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS5BCR_A, CS5BCR_D
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write32 CS6BCR_A, CS6BCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS1WCR_A, CS1WCR_D
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write32 CS2WCR_A, CS2WCR_D
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write32 CS4WCR_A, CS4WCR_D
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write32 CS5WCR_A, CS5WCR_D
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write32 CS6WCR_A, CS6WCR_D
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write32 CS5PCR_A, CS5PCR_D
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write32 CS6PCR_A, CS6PCR_D
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mov.l DELAY200_D, r3
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delay_loop_200:
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dt r3
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bf delay_loop_200
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nop
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write16 PSEL0_A, PSEL0_D
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write16 PSEL1_A, PSEL1_D
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write32 ICR0_A, ICR0_D
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stc sr, r0 /* BL bit off(init=ON) */
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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nop
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.align 2
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DELAY60_D: .long 60
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DELAY200_D: .long 17800
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CCR_A: .long 0xFF00001C
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MMUCR_A: .long 0xFF000010
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RAMCR_A: .long 0xFF000074
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/* Low power mode control */
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MSTPCR0_A: .long 0xFFC80030
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MSTPCR1_A: .long 0xFFC80038
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/* RWBT */
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WDTST_A: .long 0xFFCC0000
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WDTCSR_A: .long 0xFFCC0004
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WDTBST_A: .long 0xFFCC0008
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/* BSC */
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MMSELR_A: .long 0xFE600020
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BCR_A: .long 0xFF801000
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CS0BCR_A: .long 0xFF802000
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CS1BCR_A: .long 0xFF802010
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CS2BCR_A: .long 0xFF802020
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CS4BCR_A: .long 0xFF802040
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CS5BCR_A: .long 0xFF802050
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CS6BCR_A: .long 0xFF802060
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CS0WCR_A: .long 0xFF802008
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CS1WCR_A: .long 0xFF802018
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CS2WCR_A: .long 0xFF802028
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CS4WCR_A: .long 0xFF802048
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CS5WCR_A: .long 0xFF802058
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CS6WCR_A: .long 0xFF802068
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CS5PCR_A: .long 0xFF802070
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CS6PCR_A: .long 0xFF802080
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DDRSD_START_A: .long 0xAC000000
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/* INTC */
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ICR0_A: .long 0xFFD00000
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/* DDR I/F */
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MIM8_A: .long 0xFE800008
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MIMC_A: .long 0xFE80000C
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SCR4_A: .long 0xFE800014
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STRC_A: .long 0xFE80001C
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SDR4_A: .long 0xFE800034
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SDMR00308_A: .long 0xFE900308
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SDMR00B08_A: .long 0xFE900B08
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SDMR02000_A: .long 0xFE902000
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/* GPIO */
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PSEL0_A: .long 0xFFEF0070
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PSEL1_A: .long 0xFFEF0072
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CCR_CACHE_ICI_D:.long 0x00000800
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CCR_CACHE_D_2: .long 0x00000103
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MMU_CONTROL_TI_D:.long 0x00000004
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RAMCR_D: .long 0x00000200
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MSTPCR0_D: .long 0x00000000
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MSTPCR1_D: .long 0x00000000
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MMSELR_D: .long 0xa5a50000
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BCR_D: .long 0x00000000
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CS0BCR_D: .long 0x77777770
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CS1BCR_D: .long 0x77777670
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CS2BCR_D: .long 0x77777670
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CS4BCR_D: .long 0x77777670
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CS5BCR_D: .long 0x77777670
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CS6BCR_D: .long 0x77777670
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CS0WCR_D: .long 0x7777770F
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CS1WCR_D: .long 0x22000002
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CS2WCR_D: .long 0x7777770F
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CS4WCR_D: .long 0x7777770F
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CS5WCR_D: .long 0x7777770F
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CS6WCR_D: .long 0x7777770F
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CS5PCR_D: .long 0x77000000
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CS6PCR_D: .long 0x77000000
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ICR0_D: .long 0x00E00000
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MIM8_D: .long 0x00000000
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MIMC_D1: .long 0x01d10008
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MIMC_D2: .long 0x01d10009
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MIMC_D3: .long 0x01d10209
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SCR4_D1: .long 0x00000001
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SCR4_D2: .long 0x00000002
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SCR4_D3: .long 0x00000003
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SCR4_D4: .long 0x00000004
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STRC_D: .long 0x000f3980
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SDR4_D: .long 0x00000300
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SDMR00308_D: .long 0x00000000
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SDMR00B08_D: .long 0x00000000
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SDMR02000_D: .long 0x00000000
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PSEL0_D: .word 0x00000001
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PSEL1_D: .word 0x00000244
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SR_MASK_D: .long 0xEFFFFF0F
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WDTST_D: .long 0x5A000FFF
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WDTCSR_D: .long 0xA5000000
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WDTBST_D: .long 0x55000000
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