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1ef923851a
The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards. We check the availability of the security extensions first. Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable. Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF) The core specific GIC setup is then done in the assembly routine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> |
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am33xx | ||
at91 | ||
exynos | ||
highbank | ||
mx5 | ||
mx6 | ||
omap-common | ||
omap3 | ||
omap4 | ||
omap5 | ||
rmobile | ||
s5p-common | ||
s5pc1xx | ||
socfpga | ||
tegra-common | ||
tegra20 | ||
tegra30 | ||
tegra114 | ||
u8500 | ||
vf610 | ||
zynq | ||
cache_v7.c | ||
config.mk | ||
cpu.c | ||
lowlevel_init.S | ||
Makefile | ||
nonsec_virt.S | ||
start.S | ||
syslib.c | ||
virt-v7.c |