mirror of
https://github.com/AsahiLinux/u-boot
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636 lines
16 KiB
C
636 lines
16 KiB
C
/*
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* (C) Copyright 2003
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* Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* MCF5282 additionals
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* (C) Copyright 2005
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* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*
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* MCF5275 additions
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* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#if defined(CONFIG_CMD_NET)
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#include <config.h>
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#include <net.h>
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#include <asm/fec.h>
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#endif
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#ifndef CONFIG_M5272
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/* Only 5272 Flexbus chipselect is different from the rest */
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void init_fbcs(void)
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{
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volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
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&& defined(CONFIG_SYS_CS0_CTRL))
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fbcs->csar0 = CONFIG_SYS_CS0_BASE;
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fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
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fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
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#else
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#warning "Chip Select 0 are not initialized/used"
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#endif
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
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&& defined(CONFIG_SYS_CS1_CTRL))
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fbcs->csar1 = CONFIG_SYS_CS1_BASE;
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fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
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fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
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&& defined(CONFIG_SYS_CS2_CTRL))
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fbcs->csar2 = CONFIG_SYS_CS2_BASE;
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fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
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fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
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&& defined(CONFIG_SYS_CS3_CTRL))
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fbcs->csar3 = CONFIG_SYS_CS3_BASE;
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fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
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fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
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&& defined(CONFIG_SYS_CS4_CTRL))
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fbcs->csar4 = CONFIG_SYS_CS4_BASE;
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fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
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fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
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&& defined(CONFIG_SYS_CS5_CTRL))
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fbcs->csar5 = CONFIG_SYS_CS5_BASE;
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fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
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fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
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&& defined(CONFIG_SYS_CS6_CTRL))
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fbcs->csar6 = CONFIG_SYS_CS6_BASE;
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fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
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fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
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&& defined(CONFIG_SYS_CS7_CTRL))
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fbcs->csar7 = CONFIG_SYS_CS7_BASE;
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fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
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fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
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#endif
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}
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#endif
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#if defined(CONFIG_M5253)
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
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mbar_writeByte(MCFSIM_SYPCR, 0x00);
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mbar_writeByte(MCFSIM_SWIVR, 0x0f);
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mbar_writeByte(MCFSIM_SWSR, 0x00);
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mbar_writeByte(MCFSIM_SWDICR, 0x00);
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mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
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mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
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mbar_writeByte(MCFSIM_I2CICR, 0x00);
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mbar_writeByte(MCFSIM_UART1ICR, 0x00);
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mbar_writeByte(MCFSIM_UART2ICR, 0x00);
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mbar_writeByte(MCFSIM_ICR6, 0x00);
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mbar_writeByte(MCFSIM_ICR7, 0x00);
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mbar_writeByte(MCFSIM_ICR8, 0x00);
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mbar_writeByte(MCFSIM_ICR9, 0x00);
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mbar_writeByte(MCFSIM_QSPIICR, 0x00);
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mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
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mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
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mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
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/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
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/* FlexBus Chipselect */
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init_fbcs();
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#ifdef CONFIG_FSL_I2C
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CONFIG_SYS_I2C_PINMUX_REG =
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CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
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CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
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#ifdef CONFIG_SYS_I2C2_OFFSET
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CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
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CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
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#endif
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#endif
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/* enable instruction cache now */
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icache_enable();
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}
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/*initialize higher level parts of CPU like timers */
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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/* Setup Ports: */
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switch (CONFIG_SYS_UART_PORT) {
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case 0:
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break;
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case 1:
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break;
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case 2:
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break;
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}
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}
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#endif /* #if defined(CONFIG_M5253) */
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#if defined(CONFIG_M5271)
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void cpu_init_f(void)
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{
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#ifndef CONFIG_WATCHDOG
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/* Disable the watchdog if we aren't using it */
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mbar_writeShort(MCF_WTM_WCR, 0);
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#endif
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/* FlexBus Chipselect */
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init_fbcs();
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/* Set clockspeed to 100MHz */
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mbar_writeShort(MCF_FMPLL_SYNCR,
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MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
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while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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/* Setup Ports: */
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switch (CONFIG_SYS_UART_PORT) {
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case 0:
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mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
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MCF_GPIO_PAR_UART_U0RXD);
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break;
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case 1:
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mbar_writeShort(MCF_GPIO_PAR_UART,
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MCF_GPIO_PAR_UART_U1RXD_UART1 |
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MCF_GPIO_PAR_UART_U1TXD_UART1);
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break;
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case 2:
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mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
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break;
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}
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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if (setclear) {
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/* Enable Ethernet pins */
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mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
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} else {
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}
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return 0;
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}
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#endif /* CONFIG_CMD_NET */
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#endif
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#if defined(CONFIG_M5272)
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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/* if we come from RAM we assume the CPU is
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* already initialized.
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
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volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
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volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
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sysctrl->sc_scr = CONFIG_SYS_SCR;
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sysctrl->sc_spr = CONFIG_SYS_SPR;
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/* Setup Ports: */
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gpio->gpio_pacnt = CONFIG_SYS_PACNT;
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gpio->gpio_paddr = CONFIG_SYS_PADDR;
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gpio->gpio_padat = CONFIG_SYS_PADAT;
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gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
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gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
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gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
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gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
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/* Memory Controller: */
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csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
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csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
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#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
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csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
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csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
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#endif
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#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
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csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
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csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
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#endif
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#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
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csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
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csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
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#endif
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#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
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csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
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csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
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#endif
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#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
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csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
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csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
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#endif
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#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
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csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
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csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
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#endif
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#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
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csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
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csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
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#endif
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#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
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/* enable instruction cache now */
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (CONFIG_SYS_UART_PORT) {
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case 0:
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gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
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gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
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break;
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case 1:
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gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
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gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
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break;
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}
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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if (setclear) {
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gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
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GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
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GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
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GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
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} else {
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}
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return 0;
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}
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#endif /* CONFIG_CMD_NET */
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#endif /* #if defined(CONFIG_M5272) */
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#if defined(CONFIG_M5275)
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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/*
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* if we come from RAM we assume the CPU is
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* already initialized.
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
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volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
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/* Kill watchdog so we can initialize the PLL */
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wdog_reg->wcr = 0;
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/* FlexBus Chipselect */
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init_fbcs();
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#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
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#ifdef CONFIG_FSL_I2C
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CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
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CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
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#endif
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/* enable instruction cache now */
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (CONFIG_SYS_UART_PORT) {
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case 0:
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gpio->par_uart |= UART0_ENABLE_MASK;
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break;
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case 1:
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gpio->par_uart |= UART1_ENABLE_MASK;
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break;
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case 2:
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gpio->par_uart |= UART2_ENABLE_MASK;
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break;
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}
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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struct fec_info_s *info = (struct fec_info_s *) dev->priv;
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volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
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if (setclear) {
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/* Enable Ethernet pins */
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
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gpio->par_feci2c |= 0x0F00;
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gpio->par_fec0hl |= 0xC0;
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} else {
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gpio->par_feci2c |= 0x00A0;
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gpio->par_fec1hl |= 0xC0;
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}
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} else {
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
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gpio->par_feci2c &= ~0x0F00;
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gpio->par_fec0hl &= ~0xC0;
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} else {
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gpio->par_feci2c &= ~0x00A0;
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gpio->par_fec1hl &= ~0xC0;
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}
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}
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return 0;
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}
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#endif /* CONFIG_CMD_NET */
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#endif /* #if defined(CONFIG_M5275) */
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#if defined(CONFIG_M5282)
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/*
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* Breath some life into the CPU...
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|
*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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#ifndef CONFIG_WATCHDOG
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/* disable watchdog if we aren't using it */
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MCFWTM_WCR = 0;
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#endif
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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/* Set speed /PLL */
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MCFCLOCK_SYNCR =
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MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
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MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
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while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
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MCFGPIO_PBCDPAR = 0xc0;
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/* Set up the GPIO ports */
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#ifdef CONFIG_SYS_PEPAR
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MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
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#endif
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#ifdef CONFIG_SYS_PFPAR
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MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
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#endif
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#ifdef CONFIG_SYS_PJPAR
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MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
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|
#endif
|
|
#ifdef CONFIG_SYS_PSDPAR
|
|
MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
|
|
#endif
|
|
#ifdef CONFIG_SYS_PASPAR
|
|
MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
|
|
#endif
|
|
#ifdef CONFIG_SYS_PEHLPAR
|
|
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
|
|
#endif
|
|
#ifdef CONFIG_SYS_PQSPAR
|
|
MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
|
|
#endif
|
|
#ifdef CONFIG_SYS_PTCPAR
|
|
MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
|
|
#endif
|
|
#ifdef CONFIG_SYS_PTDPAR
|
|
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
|
|
#endif
|
|
#ifdef CONFIG_SYS_PUAPAR
|
|
MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_DDRUA
|
|
MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
|
|
#endif
|
|
|
|
/* FlexBus Chipselect */
|
|
init_fbcs();
|
|
|
|
#endif /* CONFIG_MONITOR_IS_IN_RAM */
|
|
|
|
/* defer enabling cache until boot (see do_go) */
|
|
/* icache_enable(); */
|
|
}
|
|
|
|
/*
|
|
* initialize higher level parts of CPU like timers
|
|
*/
|
|
int cpu_init_r(void)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
void uart_port_conf(void)
|
|
{
|
|
/* Setup Ports: */
|
|
switch (CONFIG_SYS_UART_PORT) {
|
|
case 0:
|
|
MCFGPIO_PUAPAR &= 0xFc;
|
|
MCFGPIO_PUAPAR |= 0x03;
|
|
break;
|
|
case 1:
|
|
MCFGPIO_PUAPAR &= 0xF3;
|
|
MCFGPIO_PUAPAR |= 0x0C;
|
|
break;
|
|
case 2:
|
|
MCFGPIO_PASPAR &= 0xFF0F;
|
|
MCFGPIO_PASPAR |= 0x00A0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_CMD_NET)
|
|
int fecpin_setclear(struct eth_device *dev, int setclear)
|
|
{
|
|
if (setclear) {
|
|
MCFGPIO_PASPAR |= 0x0F00;
|
|
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
|
|
} else {
|
|
MCFGPIO_PASPAR &= 0xF0FF;
|
|
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
|
|
}
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_CMD_NET */
|
|
#endif
|
|
|
|
#if defined(CONFIG_M5249)
|
|
/*
|
|
* Breath some life into the CPU...
|
|
*
|
|
* Set up the memory map,
|
|
* initialize a bunch of registers,
|
|
* initialize the UPM's
|
|
*/
|
|
void cpu_init_f(void)
|
|
{
|
|
/*
|
|
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
|
|
* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
|
|
* which is their primary function.
|
|
* ~Jeremy
|
|
*/
|
|
mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
|
|
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
|
|
mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
|
|
mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
|
|
mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
|
|
mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
|
|
|
|
/*
|
|
* dBug Compliance:
|
|
* You can verify these values by using dBug's 'ird'
|
|
* (Internal Register Display) command
|
|
* ~Jeremy
|
|
*
|
|
*/
|
|
mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
|
|
mbar_writeByte(MCFSIM_SYPCR, 0x00);
|
|
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
|
|
mbar_writeByte(MCFSIM_SWSR, 0x00);
|
|
mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
|
|
mbar_writeByte(MCFSIM_SWDICR, 0x00);
|
|
mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
|
|
mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
|
|
mbar_writeByte(MCFSIM_I2CICR, 0x00);
|
|
mbar_writeByte(MCFSIM_UART1ICR, 0x00);
|
|
mbar_writeByte(MCFSIM_UART2ICR, 0x00);
|
|
mbar_writeByte(MCFSIM_ICR6, 0x00);
|
|
mbar_writeByte(MCFSIM_ICR7, 0x00);
|
|
mbar_writeByte(MCFSIM_ICR8, 0x00);
|
|
mbar_writeByte(MCFSIM_ICR9, 0x00);
|
|
mbar_writeByte(MCFSIM_QSPIICR, 0x00);
|
|
|
|
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
|
|
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
|
|
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
|
|
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
|
|
|
|
/* Setup interrupt priorities for gpio7 */
|
|
/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
|
|
|
|
/* IDE Config registers */
|
|
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
|
|
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
|
|
|
|
/* FlexBus Chipselect */
|
|
init_fbcs();
|
|
|
|
/* enable instruction cache now */
|
|
icache_enable();
|
|
}
|
|
|
|
/*
|
|
* initialize higher level parts of CPU like timers
|
|
*/
|
|
int cpu_init_r(void)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
void uart_port_conf(void)
|
|
{
|
|
/* Setup Ports: */
|
|
switch (CONFIG_SYS_UART_PORT) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
break;
|
|
}
|
|
}
|
|
#endif /* #if defined(CONFIG_M5249) */
|