mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-20 03:38:43 +00:00
230fe9b202
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
78 lines
1.7 KiB
C
78 lines
1.7 KiB
C
/*
|
|
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
|
* All rights reserved.
|
|
*
|
|
* This file contains only support functions used also by the SoCFPGA
|
|
* platform code, the real meat is located in drivers/fpga/socfpga.c .
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/errno.h>
|
|
#include <asm/arch/fpga_manager.h>
|
|
#include <asm/arch/reset_manager.h>
|
|
#include <asm/arch/system_manager.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
/* Timeout count */
|
|
#define FPGA_TIMEOUT_CNT 0x1000000
|
|
|
|
static struct socfpga_fpga_manager *fpgamgr_regs =
|
|
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
|
|
|
|
/* Check whether FPGA Init_Done signal is high */
|
|
static int is_fpgamgr_initdone_high(void)
|
|
{
|
|
unsigned long val;
|
|
|
|
val = readl(&fpgamgr_regs->gpio_ext_porta);
|
|
return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
|
|
}
|
|
|
|
/* Get the FPGA mode */
|
|
int fpgamgr_get_mode(void)
|
|
{
|
|
unsigned long val;
|
|
|
|
val = readl(&fpgamgr_regs->stat);
|
|
return val & FPGAMGRREGS_STAT_MODE_MASK;
|
|
}
|
|
|
|
/* Check whether FPGA is ready to be accessed */
|
|
int fpgamgr_test_fpga_ready(void)
|
|
{
|
|
/* Check for init done signal */
|
|
if (!is_fpgamgr_initdone_high())
|
|
return 0;
|
|
|
|
/* Check again to avoid false glitches */
|
|
if (!is_fpgamgr_initdone_high())
|
|
return 0;
|
|
|
|
if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
/* Poll until FPGA is ready to be accessed or timeout occurred */
|
|
int fpgamgr_poll_fpga_ready(void)
|
|
{
|
|
unsigned long i;
|
|
|
|
/* If FPGA is blank, wait till WD invoke warm reset */
|
|
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
|
|
/* check for init done signal */
|
|
if (!is_fpgamgr_initdone_high())
|
|
continue;
|
|
/* check again to avoid false glitches */
|
|
if (!is_fpgamgr_initdone_high())
|
|
continue;
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|