mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-13 16:37:30 +00:00
cc32fd911a
The definition follows the DSA binding in kernel and describes the switch, its ports and PHYs. The switch node has the same structure as in Linux and this patch enables it (and relevant ports) for the LS1028A RDB board. ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028A, it is not used in U-Boot and was disabled. Ethernet port aliases were also added to better manage the multitude of ports available now. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc>
203 lines
2.4 KiB
Text
203 lines
2.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* NXP ls1028ARDB device tree source
|
|
*
|
|
* Copyright 2019 NXP
|
|
*
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "fsl-ls1028a.dtsi"
|
|
|
|
/ {
|
|
model = "NXP Layerscape 1028a RDB Board";
|
|
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
|
|
aliases {
|
|
spi0 = &fspi;
|
|
eth0 = &enetc0;
|
|
eth1 = &enetc2;
|
|
eth2 = &mscc_felix_port0;
|
|
eth3 = &mscc_felix_port1;
|
|
eth4 = &mscc_felix_port2;
|
|
eth5 = &mscc_felix_port3;
|
|
};
|
|
};
|
|
|
|
&dspi0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&dspi1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&dspi2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&esdhc0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&esdhc1 {
|
|
status = "okay";
|
|
mmc-hs200-1_8v;
|
|
};
|
|
|
|
&fspi {
|
|
status = "okay";
|
|
|
|
mt35xu02g0: flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "jedec,spi-nor";
|
|
spi-max-frequency = <50000000>;
|
|
reg = <0>;
|
|
spi-rx-bus-width = <8>;
|
|
spi-tx-bus-width = <1>;
|
|
};
|
|
};
|
|
|
|
&i2c0 {
|
|
status = "okay";
|
|
u-boot,dm-pre-reloc;
|
|
|
|
i2c-mux@77 {
|
|
|
|
compatible = "nxp,pca9547";
|
|
reg = <0x77>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x3>;
|
|
|
|
rtc@51 {
|
|
compatible = "pcf2127-rtc";
|
|
reg = <0x51>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c4 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c5 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c6 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c7 {
|
|
status = "okay";
|
|
};
|
|
|
|
&sata {
|
|
status = "okay";
|
|
};
|
|
|
|
&serial0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&serial1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&enetc0 {
|
|
status = "okay";
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&rdb_phy0>;
|
|
};
|
|
|
|
&enetc2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mscc_felix {
|
|
status = "okay";
|
|
};
|
|
|
|
&mscc_felix_port0 {
|
|
label = "swp0";
|
|
phy-handle = <&sw_phy0>;
|
|
phy-mode = "qsgmii";
|
|
status = "okay";
|
|
};
|
|
|
|
&mscc_felix_port1 {
|
|
label = "swp1";
|
|
phy-handle = <&sw_phy1>;
|
|
phy-mode = "qsgmii";
|
|
status = "okay";
|
|
};
|
|
|
|
&mscc_felix_port2 {
|
|
label = "swp2";
|
|
phy-handle = <&sw_phy2>;
|
|
phy-mode = "qsgmii";
|
|
status = "okay";
|
|
};
|
|
|
|
&mscc_felix_port3 {
|
|
label = "swp3";
|
|
phy-handle = <&sw_phy3>;
|
|
phy-mode = "qsgmii";
|
|
status = "okay";
|
|
};
|
|
|
|
&mscc_felix_port4 {
|
|
ethernet = <&enetc2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&mdio0 {
|
|
status = "okay";
|
|
rdb_phy0: phy@2 {
|
|
reg = <2>;
|
|
};
|
|
|
|
/* VSC8514 QSGMII PHY */
|
|
sw_phy0: phy@10 {
|
|
reg = <0x10>;
|
|
};
|
|
|
|
sw_phy1: phy@11 {
|
|
reg = <0x11>;
|
|
};
|
|
|
|
sw_phy2: phy@12 {
|
|
reg = <0x12>;
|
|
};
|
|
|
|
sw_phy3: phy@13 {
|
|
reg = <0x13>;
|
|
};
|
|
};
|