mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
573687c3be
Synchronize the Amlogic Meson Video driver back with the latest
DRM misc tree, adding G12A platform support, from the latest commit:
528a25d040bc ("drm: meson: use match data to detect vpu compatibility")
The sync includes the following changes from Linux adapted to U-Boot:
- Add support for VIC alternate timings
- Switch PLL to 5.94GHz base for 297Mhz pixel clock
- Add registers for G12A SoC
- Add G12A Support for VPP setup
- Add G12A Support for VIU setup
- Add G12A support for OSD1 Plane
- Add G12A support for plane handling in CRTC driver
- Add G12A support for CVBS Encoder
- Add G12A Video Clock setup
- Add G12A support for the DW-HDMI Glue
- fix G12A HDMI PLL settings for 4K60 1000/1001 variations
- fix primary plane disabling
- fix G12A primary plane disabling
- mask value when writing bits relaxed
- crtc: drv: vpp: viu: venc: use proper macros instead of magic constants
- global clean-up
- add macro used to enable HDMI PLL
- venc: set the correct macrovision max amplitude value
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
99 lines
2.5 KiB
C
99 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Amlogic Meson Video Processing Unit driver
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*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef __MESON_VPU_H__
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#define __MESON_VPU_H__
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#include <common.h>
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#include <dm.h>
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#include <video.h>
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#include <display.h>
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#include <linux/io.h>
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#include <linux/bitfield.h>
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#include "meson_registers.h"
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enum {
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/* Maximum size we support */
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VPU_MAX_WIDTH = 3840,
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VPU_MAX_HEIGHT = 2160,
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VPU_MAX_LOG2_BPP = VIDEO_BPP32,
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};
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enum vpu_compatible {
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VPU_COMPATIBLE_GXBB = 0,
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VPU_COMPATIBLE_GXL = 1,
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VPU_COMPATIBLE_GXM = 2,
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VPU_COMPATIBLE_G12A = 3,
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};
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struct meson_vpu_priv {
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struct udevice *dev;
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void __iomem *io_base;
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void __iomem *hhi_base;
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void __iomem *dmc_base;
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};
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static inline bool meson_vpu_is_compatible(struct meson_vpu_priv *priv,
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enum vpu_compatible family)
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{
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enum vpu_compatible compat = dev_get_driver_data(priv->dev);
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return compat == family;
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}
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#define hhi_update_bits(offset, mask, value) \
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writel_bits(mask, value, priv->hhi_base + offset)
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#define hhi_write(offset, value) \
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writel(value, priv->hhi_base + offset)
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#define hhi_read(offset) \
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readl(priv->hhi_base + offset)
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#define dmc_update_bits(offset, mask, value) \
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writel_bits(mask, value, priv->dmc_base + offset)
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#define dmc_write(offset, value) \
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writel(value, priv->dmc_base + offset)
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#define dmc_read(offset) \
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readl(priv->dmc_base + offset)
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#define MESON_CANVAS_ID_OSD1 0x4e
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/* Canvas configuration. */
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#define MESON_CANVAS_WRAP_NONE 0x00
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#define MESON_CANVAS_WRAP_X 0x01
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#define MESON_CANVAS_WRAP_Y 0x02
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#define MESON_CANVAS_BLKMODE_LINEAR 0x00
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#define MESON_CANVAS_BLKMODE_32x32 0x01
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#define MESON_CANVAS_BLKMODE_64x64 0x02
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void meson_canvas_setup(struct meson_vpu_priv *priv,
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u32 canvas_index, u32 addr,
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u32 stride, u32 height,
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unsigned int wrap,
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unsigned int blkmode);
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/* Mux VIU/VPP to ENCI */
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#define MESON_VIU_VPP_MUX_ENCI 0x5
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/* Mux VIU/VPP to ENCP */
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#define MESON_VIU_VPP_MUX_ENCP 0xA
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void meson_vpp_setup_mux(struct meson_vpu_priv *priv, unsigned int mux);
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void meson_vpu_init(struct udevice *dev);
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void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced);
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bool meson_venc_hdmi_supported_mode(const struct display_timing *mode);
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void meson_vpu_setup_venc(struct udevice *dev,
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const struct display_timing *mode, bool is_cvbs);
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bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv,
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unsigned int freq);
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void meson_vpu_setup_vclk(struct udevice *dev,
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const struct display_timing *mode, bool is_cvbs);
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#endif
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