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https://github.com/AsahiLinux/u-boot
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1e94b46f73
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
172 lines
3.9 KiB
C
172 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Meson G12A USB2 PHY driver
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*
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* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstron@baylibre.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <linux/delay.h>
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#include <linux/printk.h>
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#include <power/regulator.h>
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#include <reset.h>
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#include <clk.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#define PHY_CTRL_R0 0x0
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#define PHY_CTRL_R1 0x4
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#define PHY_CTRL_R2 0x8
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#define PHY_CTRL_R3 0xc
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#define PHY_CTRL_R4 0x10
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#define PHY_CTRL_R5 0x14
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#define PHY_CTRL_R6 0x18
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#define PHY_CTRL_R7 0x1c
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#define PHY_CTRL_R8 0x20
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#define PHY_CTRL_R9 0x24
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#define PHY_CTRL_R10 0x28
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#define PHY_CTRL_R11 0x2c
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#define PHY_CTRL_R12 0x30
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#define PHY_CTRL_R13 0x34
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#define PHY_CTRL_R14 0x38
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#define PHY_CTRL_R15 0x3c
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#define PHY_CTRL_R16 0x40
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#define PHY_CTRL_R17 0x44
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#define PHY_CTRL_R18 0x48
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#define PHY_CTRL_R19 0x4c
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#define PHY_CTRL_R20 0x50
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#define PHY_CTRL_R21 0x54
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#define PHY_CTRL_R22 0x58
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#define PHY_CTRL_R23 0x5c
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#define RESET_COMPLETE_TIME 1000
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#define PLL_RESET_COMPLETE_TIME 100
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struct phy_meson_g12a_usb2_priv {
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struct regmap *regmap;
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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struct reset_ctl reset;
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};
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static int phy_meson_g12a_usb2_init(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
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int ret;
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ret = reset_assert(&priv->reset);
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udelay(1);
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ret |= reset_deassert(&priv->reset);
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if (ret)
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return ret;
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udelay(RESET_COMPLETE_TIME);
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/* usb2_otg_aca_en == 0 */
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regmap_update_bits(priv->regmap, PHY_CTRL_R21, BIT(2), 0);
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/* PLL Setup : 24MHz * 20 / 1 = 480MHz */
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regmap_write(priv->regmap, PHY_CTRL_R16, 0x39400414);
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regmap_write(priv->regmap, PHY_CTRL_R17, 0x927e0000);
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regmap_write(priv->regmap, PHY_CTRL_R18, 0xac5f49e5);
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udelay(PLL_RESET_COMPLETE_TIME);
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/* UnReset PLL */
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regmap_write(priv->regmap, PHY_CTRL_R16, 0x19400414);
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/* PHY Tuning */
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regmap_write(priv->regmap, PHY_CTRL_R20, 0xfe18);
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regmap_write(priv->regmap, PHY_CTRL_R4, 0x8000fff);
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/* Tuning Disconnect Threshold */
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regmap_write(priv->regmap, PHY_CTRL_R3, 0x34);
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/* Analog Settings */
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regmap_write(priv->regmap, PHY_CTRL_R14, 0);
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regmap_write(priv->regmap, PHY_CTRL_R13, 0x78000);
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return 0;
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}
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static int phy_meson_g12a_usb2_exit(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
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int ret;
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ret = reset_assert(&priv->reset);
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if (ret)
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return ret;
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return 0;
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}
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struct phy_ops meson_g12a_usb2_phy_ops = {
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.init = phy_meson_g12a_usb2_init,
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.exit = phy_meson_g12a_usb2_exit,
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};
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int meson_g12a_usb2_phy_probe(struct udevice *dev)
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{
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struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
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if (ret)
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return ret;
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ret = reset_get_by_index(dev, 0, &priv->reset);
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if (ret == -ENOTSUPP)
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return 0;
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else if (ret)
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return ret;
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ret = reset_deassert(&priv->reset);
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if (ret) {
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reset_release_all(&priv->reset, 1);
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return ret;
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}
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
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pr_err("failed to enable PHY clock\n");
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clk_free(&priv->clk);
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return ret;
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}
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#endif
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return 0;
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}
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static const struct udevice_id meson_g12a_usb2_phy_ids[] = {
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{ .compatible = "amlogic,g12a-usb2-phy" },
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{ }
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};
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U_BOOT_DRIVER(meson_g12a_usb2_phy) = {
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.name = "meson_g12a_usb2_phy",
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.id = UCLASS_PHY,
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.of_match = meson_g12a_usb2_phy_ids,
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.probe = meson_g12a_usb2_phy_probe,
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.ops = &meson_g12a_usb2_phy_ops,
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.priv_auto = sizeof(struct phy_meson_g12a_usb2_priv),
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};
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