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https://github.com/AsahiLinux/u-boot
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3f1250a9e2
1. Enable MTK SPI NOR controller driver on mt7622 & mt7629. 2. Enable quad mode for read and single mode for write. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
352 lines
9.3 KiB
Text
352 lines
9.3 KiB
Text
/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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#include <dt-bindings/clock/mt7629-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/mt7629-power.h>
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#include <dt-bindings/reset/mt7629-reset.h>
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#include <dt-bindings/phy/phy.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "mediatek,mt7629";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clock-frequency = <1250000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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clock-frequency = <1250000000>;
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};
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};
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clk20m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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clock-output-names = "clk20m";
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};
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clk40m: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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clock-output-names = "clkxtal";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <20000000>;
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arm,cpu-registers-not-fw-configured;
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};
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infracfg: syscon@10000000 {
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compatible = "mediatek,mt7629-infracfg", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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pericfg: syscon@10002000 {
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compatible = "mediatek,mt7629-pericfg", "syscon";
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reg = <0x10002000 0x1000>;
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#clock-cells = <1>;
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};
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timer0: timer@10004000 {
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compatible = "mediatek,timer";
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reg = <0x10004000 0x80>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
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<&topckgen CLK_TOP_10M_SEL>;
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clock-names = "mux", "src";
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7629-scpsys";
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reg = <0x10006000 0x1000>;
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clocks = <&topckgen CLK_TOP_HIF_SEL>;
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clock-names = "hif_sel";
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assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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#power-domain-cells = <1>;
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infracfg = <&infracfg>;
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};
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mcucfg: syscon@10200000 {
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compatible = "mediatek,mt7629-mcucfg", "syscon";
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reg = <0x10200000 0x1000>;
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#clock-cells = <1>;
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};
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sysirq: interrupt-controller@10200a80 {
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compatible = "mediatek,sysirq";
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reg = <0x10200a80 0x20>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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dramc: dramc@10203000 {
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compatible = "mediatek,mt7629-dramc";
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reg = <0x10203000 0x600>, /* EMI */
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<0x10213000 0x1000>, /* DDRPHY */
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<0x10214000 0xd00>; /* DRAMC_AO */
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clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
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<&topckgen CLK_TOP_SYSPLL1_D8>,
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<&topckgen CLK_TOP_MEM_SEL>,
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<&topckgen CLK_TOP_DMPLL>;
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clock-names = "phy", "phy_mux", "mem", "mem_mux";
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};
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apmixedsys: clock-controller@10209000 {
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compatible = "mediatek,mt7629-apmixedsys";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: clock-controller@10210000 {
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compatible = "mediatek,mt7629-topckgen";
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reg = <0x10210000 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@10212000 {
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compatible = "mediatek,wdt";
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reg = <0x10212000 0x600>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>;
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#reset-cells = <1>;
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status = "disabled";
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&watchdog>;
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};
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pinctrl: pinctrl@10217000 {
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compatible = "mediatek,mt7629-pinctrl";
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reg = <0x10217000 0x8000>;
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10310000 0x1000>,
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<0x10320000 0x1000>,
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<0x10340000 0x2000>,
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<0x10360000 0x2000>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,hsuart";
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reg = <0x11002000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART0_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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};
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uart1: serial@11003000 {
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compatible = "mediatek,hsuart";
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reg = <0x11003000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART1_PD>;
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clock-names = "baud", "bus";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,hsuart";
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reg = <0x11004000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART2_PD>;
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clock-names = "baud", "bus";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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status = "disabled";
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};
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snfi: snfi@1100d000 {
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compatible = "mediatek,mtk-snfi-spi";
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reg = <0x1100d000 0x2000>;
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clocks = <&pericfg CLK_PERI_NFI_PD>,
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<&pericfg CLK_PERI_SNFI_PD>;
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clock-names = "nfi_clk", "pad_clk";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
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<&topckgen CLK_TOP_NFI_INFRA_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
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<&topckgen CLK_TOP_UNIVPLL2_D8>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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snor: snor@11014000 {
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compatible = "mediatek,mtk-snor";
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reg = <0x11014000 0x1000>;
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clocks = <&pericfg CLK_PERI_FLASH_PD>,
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<&topckgen CLK_TOP_FLASH_SEL>;
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clock-names = "spi", "sf";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ssusbsys: ssusbsys@1a000000 {
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compatible = "mediatek,mt7629-ssusbsys", "syscon";
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reg = <0x1a000000 0x1000>;
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#clock-cells = <1>;
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};
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xhci: usb@1a0c0000 {
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compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci";
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reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>;
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reg-names = "mac", "ippc";
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power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
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clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
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<&ssusbsys CLK_SSUSB_REF_EN>,
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<&ssusbsys CLK_SSUSB_MCU_EN>,
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<&ssusbsys CLK_SSUSB_DMA_EN>;
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clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
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phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
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status = "disabled";
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};
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u3phy: usb-phy@1a0c4000 {
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compatible = "mediatek,mt7629-tphy", "mediatek,generic-tphy-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1a0c4000 0x1000>;
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status = "disabled";
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u2port0: usb-phy@0 {
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reg = <0x0 0x0700>;
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#phy-cells = <1>;
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clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
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clock-names = "ref";
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};
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u3port0: usb-phy@700 {
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reg = <0x0700 0x0700>;
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#phy-cells = <1>;
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};
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};
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7629-ethsys", "syscon";
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reg = <0x1b000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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eth: ethernet@1b100000 {
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compatible = "mediatek,mt7629-eth", "syscon";
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reg = <0x1b100000 0x20000>;
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clocks = <&topckgen CLK_TOP_ETH_SEL>,
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<&topckgen CLK_TOP_F10M_REF_SEL>,
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<ðsys CLK_ETH_ESW_EN>,
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<ðsys CLK_ETH_GP0_EN>,
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<ðsys CLK_ETH_GP1_EN>,
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<ðsys CLK_ETH_GP2_EN>,
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<ðsys CLK_ETH_FE_EN>,
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<&sgmiisys0 CLK_SGMII_TX_EN>,
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<&sgmiisys0 CLK_SGMII_RX_EN>,
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<&sgmiisys0 CLK_SGMII_CDR_REF>,
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<&sgmiisys0 CLK_SGMII_CDR_FB>,
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<&sgmiisys1 CLK_SGMII_TX_EN>,
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<&sgmiisys1 CLK_SGMII_RX_EN>,
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<&sgmiisys1 CLK_SGMII_CDR_REF>,
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<&sgmiisys1 CLK_SGMII_CDR_FB>,
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<&apmixedsys CLK_APMIXED_SGMIPLL>,
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<&apmixedsys CLK_APMIXED_ETH2PLL>;
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clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
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"fe", "sgmii_tx250m", "sgmii_rx250m",
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"sgmii_cdr_ref", "sgmii_cdr_fb",
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"sgmii2_tx250m", "sgmii2_rx250m",
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"sgmii2_cdr_ref", "sgmii2_cdr_fb",
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"sgmii_ck", "eth2pll";
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assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
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<&topckgen CLK_TOP_F10M_REF_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
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<&topckgen CLK_TOP_SGMIIPLL_D2>;
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power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
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resets = <ðsys ETHSYS_FE_RST>;
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reset-names = "fe";
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys0>;
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mediatek,infracfg = <&infracfg>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sgmiisys0: syscon@1b128000 {
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compatible = "mediatek,mt7629-sgmiisys", "syscon";
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reg = <0x1b128000 0x1000>;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@1b130000 {
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compatible = "mediatek,mt7629-sgmiisys", "syscon";
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reg = <0x1b130000 0x1000>;
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#clock-cells = <1>;
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};
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pwm: pwm@11006000 {
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compatible = "mediatek,mt7629-pwm";
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reg = <0x11006000 0x1000>;
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#clock-cells = <1>;
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#pwm-cells = <2>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&pericfg CLK_PERI_PWM_PD>,
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<&pericfg CLK_PERI_PWM1_PD>;
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clock-names = "top", "main", "pwm1";
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assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>;
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status = "disabled";
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};
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};
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