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38d1a18750
Add properties related to eMMC HS400 mode for esdhc1. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
64 lines
1.1 KiB
Text
64 lines
1.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17
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*
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* Some assumptions are made:
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* * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6)
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*
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* Copyright 2020-2021 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac3 {
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status = "okay";
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phy-handle = <&inphi_phy0>;
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phy-connection-type = "25g-aui";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&inphi_phy1>;
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phy-connection-type = "25g-aui";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&inphi_phy2>;
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phy-connection-type = "25g-aui";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&inphi_phy3>;
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phy-connection-type = "25g-aui";
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};
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&emdio1_slot1 {
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inphi_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0210.7440";
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reg = <0x0>;
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};
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inphi_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id0210.7440";
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reg = <0x1>;
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};
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inphi_phy2: ethernet-phy@2 {
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compatible = "ethernet-phy-id0210.7440";
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reg = <0x2>;
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};
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inphi_phy3: ethernet-phy@3 {
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compatible = "ethernet-phy-id0210.7440";
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reg = <0x3>;
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};
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};
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&esdhc1 {
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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bus-width = <8>;
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};
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