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https://github.com/AsahiLinux/u-boot
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476dcb6b43
Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value, move it to SoC's own Kconfig, and add address for rk3128 and rk3328 so that all SoCs have available address. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
283 lines
8.9 KiB
Text
283 lines
8.9 KiB
Text
if ARCH_ROCKCHIP
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config ROCKCHIP_RK3036
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bool "Support Rockchip RK3036"
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select CPU_V7A
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select SUPPORT_SPL
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select SPL
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imply USB_FUNCTION_ROCKUSB
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imply CMD_ROCKUSB
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help
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The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
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including NEON and GPU, Mali-400 graphics, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
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config ROCKCHIP_RK3128
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bool "Support Rockchip RK3128"
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select CPU_V7A
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help
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The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
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including NEON and GPU, Mali-400 graphics, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
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config ROCKCHIP_RK3188
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bool "Support Rockchip RK3188"
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select CPU_V7A
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select SPL_BOARD_INIT if SPL
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select SUPPORT_SPL
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select SPL
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select SPL_CLK
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select SPL_REGMAP
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select SPL_SYSCON
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select SPL_RAM
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select SPL_DRIVERS_MISC_SUPPORT
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select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
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select BOARD_LATE_INIT
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select ROCKCHIP_BROM_HELPER
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help
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The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
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including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
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video interfaces, several memory options and video codec support.
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Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
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UART, SPI, I2C and PWMs.
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config ROCKCHIP_RK322X
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bool "Support Rockchip RK3228/RK3229"
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select CPU_V7A
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select SUPPORT_SPL
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select SUPPORT_TPL
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select SPL
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select SPL_DM
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select SPL_OF_LIBFDT
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select TPL
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select TPL_DM
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select TPL_OF_LIBFDT
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select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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select SPL_DRIVERS_MISC_SUPPORT
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imply SPL_SERIAL_SUPPORT
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imply TPL_SERIAL_SUPPORT
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select ROCKCHIP_BROM_HELPER
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select TPL_LIBCOMMON_SUPPORT
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select TPL_LIBGENERIC_SUPPORT
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help
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The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
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including NEON and GPU, Mali-400 graphics, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
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config ROCKCHIP_RK3288
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bool "Support Rockchip RK3288"
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select CPU_V7A
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select SPL_BOARD_INIT if SPL
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select SUPPORT_SPL
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select SPL
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select SUPPORT_TPL
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imply TPL_BOOTROM_SUPPORT
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imply TPL_CLK
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imply TPL_DM
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imply TPL_DRIVERS_MISC_SUPPORT
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imply TPL_LIBCOMMON_SUPPORT
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imply TPL_LIBGENERIC_SUPPORT
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imply TPL_NEEDS_SEPARATE_TEXT_BASE
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imply TPL_NEEDS_SEPARATE_STACK
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imply TPL_OF_CONTROL
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imply TPL_OF_PLATDATA
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imply TPL_RAM
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imply TPL_REGMAP
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imply TPL_SERIAL_SUPPORT
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imply TPL_SYSCON
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imply USB_FUNCTION_ROCKUSB
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imply CMD_ROCKUSB
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help
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The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
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including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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video interfaces supporting HDMI and eDP, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3328
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bool "Support Rockchip RK3328"
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select ARM64
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select SUPPORT_SPL
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select SPL
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imply SPL_SERIAL_SUPPORT
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imply SPL_SEPARATE_BSS
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select ENABLE_ARM_SOC_BOOT0_HOOK
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select DEBUG_UART_BOARD_INIT
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select SYS_NS16550
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help
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The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
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including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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video interfaces supporting HDMI and eDP, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3368
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bool "Support Rockchip RK3368"
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select ARM64
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select SUPPORT_SPL
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select SUPPORT_TPL
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select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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imply SPL_SEPARATE_BSS
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imply SPL_SERIAL_SUPPORT
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imply TPL_SERIAL_SUPPORT
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help
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The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
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into a big and little cluster with 4 cores each) Cortex-A53 including
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AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
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(for the little cluster), PowerVR G6110 based graphics, one video
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output processor supporting LVDS/HDMI/eDP, several DDR3 options and
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video codec support.
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On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
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I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3399
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bool "Support Rockchip RK3399"
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select ARM64
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select SUPPORT_SPL
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select SUPPORT_TPL
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select SPL
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select SPL_ATF
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select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
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select SPL_BOARD_INIT if SPL
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select SPL_LOAD_FIT
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select SPL_CLK if SPL
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select SPL_PINCTRL if SPL
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select SPL_RAM if SPL
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select SPL_REGMAP if SPL
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select SPL_SYSCON if SPL
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select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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select SPL_SEPARATE_BSS
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select SPL_SERIAL_SUPPORT
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select SPL_DRIVERS_MISC_SUPPORT
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select CLK
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select FIT
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select PINCTRL
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select RAM
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select REGMAP
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select SYSCON
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select DM_PMIC
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select DM_REGULATOR_FIXED
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select BOARD_LATE_INIT
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select ROCKCHIP_BROM_HELPER
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imply TPL_SERIAL_SUPPORT
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imply TPL_LIBCOMMON_SUPPORT
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imply TPL_LIBGENERIC_SUPPORT
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imply TPL_SYS_MALLOC_SIMPLE
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imply TPL_BOARD_INIT
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imply TPL_BOOTROM_SUPPORT
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imply TPL_DRIVERS_MISC_SUPPORT
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imply TPL_OF_CONTROL
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imply TPL_DM
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imply TPL_REGMAP
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imply TPL_SYSCON
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imply TPL_RAM
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imply TPL_CLK
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imply TPL_TINY_MEMSET
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help
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The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
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and quad-core Cortex-A53.
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including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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video interfaces supporting HDMI and eDP, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RV1108
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bool "Support Rockchip RV1108"
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select CPU_V7A
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help
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The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
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and a DSP.
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config ROCKCHIP_USB_UART
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bool "Route uart output to usb pins"
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help
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Rockchip SoCs have the ability to route the signals of the debug
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uart through the d+ and d- pins of a specific usb phy to enable
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some form of closed-case debugging. With this option supported
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SoCs will enable this routing as a debug measure.
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config SPL_ROCKCHIP_BACK_TO_BROM
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bool "SPL returns to bootrom"
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default y if ROCKCHIP_RK3036
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select ROCKCHIP_BROM_HELPER
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depends on SPL
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help
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Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
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SPL will return to the boot rom, which will then load the U-Boot
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binary to keep going on.
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config TPL_ROCKCHIP_BACK_TO_BROM
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bool "TPL returns to bootrom"
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default y
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select ROCKCHIP_BROM_HELPER
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depends on TPL
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help
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Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
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SPL will return to the boot rom, which will then load the U-Boot
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binary to keep going on.
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config ROCKCHIP_BOOT_MODE_REG
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hex "Rockchip boot mode flag register address"
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help
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The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
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according to the value from this register.
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config ROCKCHIP_SPL_RESERVE_IRAM
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hex "Size of IRAM reserved in SPL"
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default 0
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help
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SPL may need reserve memory for firmware loaded by SPL, whose load
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address is in IRAM and may overlay with SPL text area if not
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reserved.
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config ROCKCHIP_BROM_HELPER
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bool
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config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
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bool "SPL requires early-return (for RK3188-style BROM) to BROM"
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depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
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help
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Some Rockchip BROM variants (e.g. on the RK3188) load the
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first stage in segments and enter multiple times. E.g. on
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the RK3188, the first 1KB of the first stage are loaded
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first and entered; after returning to the BROM, the
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remainder of the first stage is loaded, but the BROM
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re-enters at the same address/to the same code as previously.
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This enables support code in the BOOT0 hook for the SPL stage
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to allow multiple entries.
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config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
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bool "TPL requires early-return (for RK3188-style BROM) to BROM"
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depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
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help
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Some Rockchip BROM variants (e.g. on the RK3188) load the
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first stage in segments and enter multiple times. E.g. on
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the RK3188, the first 1KB of the first stage are loaded
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first and entered; after returning to the BROM, the
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remainder of the first stage is loaded, but the BROM
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re-enters at the same address/to the same code as previously.
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This enables support code in the BOOT0 hook for the TPL stage
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to allow multiple entries.
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config SPL_MMC_SUPPORT
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default y if !SPL_ROCKCHIP_BACK_TO_BROM
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source "arch/arm/mach-rockchip/rk3036/Kconfig"
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source "arch/arm/mach-rockchip/rk3128/Kconfig"
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source "arch/arm/mach-rockchip/rk3188/Kconfig"
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source "arch/arm/mach-rockchip/rk322x/Kconfig"
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source "arch/arm/mach-rockchip/rk3288/Kconfig"
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source "arch/arm/mach-rockchip/rk3328/Kconfig"
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source "arch/arm/mach-rockchip/rk3368/Kconfig"
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source "arch/arm/mach-rockchip/rk3399/Kconfig"
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source "arch/arm/mach-rockchip/rv1108/Kconfig"
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endif
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