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1e566bc6db
Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of bytes that can be in a write transaction. Support this by breaking the writes into multiple transactions. Signed-off-by: Simon Glass <sjg@chromium.org> |
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.. | ||
nand | ||
onenand | ||
spi | ||
ubi | ||
at45.c | ||
cfi_flash.c | ||
cfi_mtd.c | ||
dataflash.c | ||
ftsmc020.c | ||
jedec_flash.c | ||
Makefile | ||
mtdconcat.c | ||
mtdcore.c | ||
mtdpart.c | ||
mw_eeprom.c | ||
st_smi.c |