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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
129 lines
4.9 KiB
C
129 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* This header file describes this specific Xtensa processor's TIE extensions
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* that extend basic Xtensa core functionality. It is customized to this
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* Xtensa processor configuration.
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* This file is autogenerated, please do not edit.
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*
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* Copyright (C) 1999-2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_CORE_TIE_H
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#define _XTENSA_CORE_TIE_H
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#define XCHAL_CP_NUM 1 /* number of coprocessors */
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#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
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#define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
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#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
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/* Basic parameters of each coprocessor: */
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#define XCHAL_CP7_NAME "XTIOP"
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#define XCHAL_CP7_IDENT XTIOP
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#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
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#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
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#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
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/* Filler info for unassigned coprocessors, to simplify arrays etc: */
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#define XCHAL_CP0_SA_SIZE 0
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#define XCHAL_CP0_SA_ALIGN 1
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#define XCHAL_CP1_SA_SIZE 0
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#define XCHAL_CP1_SA_ALIGN 1
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#define XCHAL_CP2_SA_SIZE 0
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#define XCHAL_CP2_SA_ALIGN 1
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#define XCHAL_CP3_SA_SIZE 0
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#define XCHAL_CP3_SA_ALIGN 1
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#define XCHAL_CP4_SA_SIZE 0
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#define XCHAL_CP4_SA_ALIGN 1
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#define XCHAL_CP5_SA_SIZE 0
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#define XCHAL_CP5_SA_ALIGN 1
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#define XCHAL_CP6_SA_SIZE 0
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#define XCHAL_CP6_SA_ALIGN 1
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/* Save area for non-coprocessor optional and custom (TIE) state: */
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#define XCHAL_NCP_SA_SIZE 32
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#define XCHAL_NCP_SA_ALIGN 4
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/* Total save area for optional and custom state (NCP + CPn): */
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#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
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#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
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/*
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* Detailed contents of save areas.
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* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
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* before expanding the XCHAL_xxx_SA_LIST() macros.
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*
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* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
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* dbnum,base,regnum,bitsz,gapsz,reset,x...)
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*
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* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
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* ccused = set if used by compiler without special options or code
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* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
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* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
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* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
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* name = lowercase reg name (no quotes)
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* galign = group byte alignment (power of 2) (galign >= align)
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* align = register byte alignment (power of 2)
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* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
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* (not including any pad bytes required to galign this or next reg)
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* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
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* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
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* regnum = reg index in regfile, or special/TIE-user reg number
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* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
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* gapsz = intervening bits, if bitsz bits not stored contiguously
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* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
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* reset = register reset value (or 0 if undefined at reset)
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* x = reserved for future use (0 until then)
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*
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* To filter out certain registers, e.g. to expand only the non-global
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* registers used by the compiler, you can do something like this:
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*
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* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
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* #define SELCC0(p...)
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* #define SELCC1(abikind,p...) SELAK##abikind(p)
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* #define SELAK0(p...) REG(p)
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* #define SELAK1(p...) REG(p)
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* #define SELAK2(p...)
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* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
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* ...what you want to expand...
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*/
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#define XCHAL_NCP_SA_NUM 8
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#define XCHAL_NCP_SA_LIST(s) \
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XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
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XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
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XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
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XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
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XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
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XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
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XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
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XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
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#define XCHAL_CP0_SA_NUM 0
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#define XCHAL_CP0_SA_LIST(s) /* empty */
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#define XCHAL_CP1_SA_NUM 0
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#define XCHAL_CP1_SA_LIST(s) /* empty */
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#define XCHAL_CP2_SA_NUM 0
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#define XCHAL_CP2_SA_LIST(s) /* empty */
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#define XCHAL_CP3_SA_NUM 0
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#define XCHAL_CP3_SA_LIST(s) /* empty */
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#define XCHAL_CP4_SA_NUM 0
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#define XCHAL_CP4_SA_LIST(s) /* empty */
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#define XCHAL_CP5_SA_NUM 0
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#define XCHAL_CP5_SA_LIST(s) /* empty */
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#define XCHAL_CP6_SA_NUM 0
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#define XCHAL_CP6_SA_LIST(s) /* empty */
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#define XCHAL_CP7_SA_NUM 0
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#define XCHAL_CP7_SA_LIST(s) /* empty */
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/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
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#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
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#endif /*_XTENSA_CORE_TIE_H*/
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