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b3d97f8ce3
In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows: " RAM: DDR3L 32bits 2x4Gb 533MHz DDR invalid size : 0x4, expected 0x40000000 DRAM init failed: -22 ### ERROR ### Please RESET the board ### " Avoid this failure by not keeping any Buck regulators enabled during reset, let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3 VDD enabled during reset is ST specific, move this addition to ST specific SPL board initialization so that it wouldn't affect the DHSOM . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
36 lines
884 B
C
36 lines
884 B
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <config.h>
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#include <common.h>
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#include <power/pmic.h>
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#include <power/stpmic1.h>
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#include <asm/arch/sys_proto.h>
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#include "../common/stpmic1.h"
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/* board early initialisation in board_f: need to use global variable */
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static u32 opp_voltage_mv __section(".data");
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void board_vddcore_init(u32 voltage_mv)
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{
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if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER))
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opp_voltage_mv = voltage_mv;
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}
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int board_early_init_f(void)
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{
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if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) {
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struct udevice *dev = stpmic1_init(opp_voltage_mv);
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/* Keep vdd on during the reset cycle */
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pmic_clrsetbits(dev,
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STPMIC1_BUCKS_MRST_CR,
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STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
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STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
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}
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return 0;
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}
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