mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-16 00:03:24 +00:00
08002ffd08
Device tree alignment with Linux kernel v6.3: - f5a058023239 - ARM: dts: stm32: add i2c nodes into stm32mp131.dtsi - 8539ebb435a5 - ARM: dts: stm32: enable i2c1 and i2c5 on stm32mp135f-dk.dts - 8539ebb435a5 - ARM: dts: stm32: add spi nodes into stm32mp131.dtsi - 15f72e0da4da - ARM: dts: stm32: add pinctrl and disabled spi5 node in stm32mp135f-dk - ea99a5a02ebc - ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi - a306d8962a24 - ARM: dts: stm32: Rename mdio0 to mdio - 0a5ebb1f3367 - ARM: dts: stm32: Replace SAI format with dai-format DT property - ccdab19738a6 - ARM: dts: stm32: add adc support to stm32mp13 - 022932ab55fd - ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk - ab2806ddad9d - ARM: dts: stm32: add dummy vdd_adc regulator on stm32mp135f-dk - e46a180c060f - ARM: dts: stm32: add adc support on stm32mp135f-dk - 9ebf215fbae1 - ARM: dts: stm32: add PWR fixed regulators on stm32mp131 - 16f4ff60519a - ARM: dts: stm32: add USBPHYC and dual USB HS PHY support on stm32mp131 - 4a47f0f3e936 - ARM: dts: stm32: add UBSH EHCI and OHCI support on stm32mp131 - 2a46bb66c47f - ARM: dts: stm32: add USB OTG HS support on stm32mp131 - 9ebf215fbae1 - ARM: dts: stm32: add fixed regulators to support usb on stm32mp135f-dk - 16f4ff60519a - ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk - c4e7254cf6dc - ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk - 44978e135916 - ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13 - 4f532403b1e5 - ARM: dts: stm32: enable USB OTG in dual role mode on stm32mp135f-dk - e1f15571c96c - ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13 - 6cc71374002e - ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk - 7ffd2266bd32 - ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcor-som - 21d83512bf2b - ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcom-som - 732dbcf52f74 - ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp151a-prtt1l - 003b7c6b24f4 - ARM: dts: stm32: remove sai kernel clock on stm32mp15xx-dkx - f2b17b39bfff - ARM: dts: stm32: rename sound card on stm32mp15xx-dkx - dee3cb759d3d - ARM: dts: stm32: Remove the pins-are-numbered property - ae8cf3b48727 - ARM: dts: stm32: add i2s nodes on stm32mp131 - 619746a27bd0 - ARM: dts: stm32: add sai nodes on stm32mp131 - c5e05d08ef90 - ARM: dts: stm32: add spdifrx node on stm32mp131 - 0a5afd3ee0d0 - ARM: dts: stm32: add dfsdm node on stm32mp131 - bf9d876bea2e - ARM: dts: stm32: add timers support on stm32mp131 - a3183748371d - ARM: dts: stm32: add timer pins muxing for stm32mp135f-dk - a9060c1326bc - ARM: dts: stm32: add timers support on stm32mp135f-dk - a12154058f75 - ARM: dts: stm32: Fix User button on stm32mp135f-dk - 2f33df889e99 - ARM: dts: stm32: Use new media bus type macros - 366384e49551 - ARM: dts: stm32: Update part number NVMEM description on stm32mp131 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
261 lines
5.9 KiB
Text
261 lines
5.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
*/
|
|
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
|
|
|
&pinctrl {
|
|
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
|
|
<STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
|
|
};
|
|
};
|
|
|
|
i2c1_pins_a: i2c1-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
|
<STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
i2c1_sleep_pins_a: i2c1-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
|
<STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
|
|
};
|
|
};
|
|
|
|
i2c5_pins_a: i2c5-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
|
|
<STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
i2c5_sleep_pins_a: i2c5-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
|
|
<STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
|
|
};
|
|
};
|
|
|
|
mcp23017_pins_a: mcp23017-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('G', 12, GPIO)>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pwm3_pins_a: pwm3-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
|
|
bias-pull-down;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
pwm3_sleep_pins_a: pwm3-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
|
|
};
|
|
};
|
|
|
|
pwm4_pins_a: pwm4-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
|
|
bias-pull-down;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
pwm4_sleep_pins_a: pwm4-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
|
|
};
|
|
};
|
|
|
|
pwm8_pins_a: pwm8-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
|
|
bias-pull-down;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
pwm8_sleep_pins_a: pwm8-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
|
|
};
|
|
};
|
|
|
|
pwm14_pins_a: pwm14-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
|
|
bias-pull-down;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
pwm14_sleep_pins_a: pwm14-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
|
|
};
|
|
};
|
|
|
|
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
|
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-disable;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
slew-rate = <1>;
|
|
drive-open-drain;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
|
|
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
|
|
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
|
|
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
|
|
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
|
|
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
|
|
};
|
|
};
|
|
|
|
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
|
|
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
|
|
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
|
|
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
|
|
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
|
|
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
|
|
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
|
|
<STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-pull-up;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
slew-rate = <1>;
|
|
drive-open-drain;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
|
|
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
|
|
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
|
|
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
|
|
<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
|
|
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
|
|
};
|
|
};
|
|
|
|
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
spi5_pins_a: spi5-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
|
|
<STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <1>;
|
|
};
|
|
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
spi5_sleep_pins_a: spi5-sleep-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
|
|
<STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
|
|
<STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
|
|
};
|
|
};
|
|
|
|
stm32g0_intn_pins_a: stm32g0-intn-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
uart4_pins_a: uart4-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|