mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 16:07:30 +00:00
323846561a
The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/*
|
|
* (C) Copyright 2000-2003
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
*
|
|
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
|
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/clock.h>
|
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
#endif
|
|
|
|
int get_clocks(void)
|
|
{
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
#ifdef CONFIG_FSL_USDHC
|
|
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
#else
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
#endif
|
|
#else
|
|
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
#else
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
#endif
|
|
#endif
|
|
#endif
|
|
return 0;
|
|
}
|