mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
3c7ad8c40e
Add imx8mm_evk_fspi_defconfig to build QSPI boot image. This config is based on imx8mm_evk_defconfig with addtional config options to define FSPI Header parameters required to generate QSPI Header. Update SPL offset to include header size and overwrite IMX_CONFIG to use lpddr.cfg for FSPI. Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com> Signed-off-by: Thomas Haemmerle <thomas.haemmerle@leica-geosystems.com> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
123 lines
3.1 KiB
Text
123 lines
3.1 KiB
Text
CONFIG_ARM=y
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CONFIG_ARCH_IMX8M=y
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CONFIG_SYS_TEXT_BASE=0x40200000
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CONFIG_SYS_MALLOC_LEN=0x2000000
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CONFIG_SPL_GPIO=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x400000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
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CONFIG_SPL_TEXT_BASE=0x7E2000
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CONFIG_TARGET_IMX8MM_EVK=y
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CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
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CONFIG_SPL_MMC=y
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CONFIG_SPL_NOR_SUPPORT=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_SYS_LOAD_ADDR=0x40480000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_FIT=y
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CONFIG_FIT_EXTERNAL_OFFSET=0x3000
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CONFIG_SPL_LOAD_FIT=y
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# CONFIG_USE_SPL_FIT_GENERATOR is not set
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CONFIG_OF_SYSTEM_SETUP=y
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CONFIG_BOARD_LATE_INIT=y
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CONFIG_SPL_MAX_SIZE=0x25000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x910000
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CONFIG_SPL_BSS_MAX_SIZE=0x2000
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CONFIG_SPL_BOARD_INIT=y
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK=0x920000
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CONFIG_SYS_SPL_MALLOC=y
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CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
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CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
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CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
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CONFIG_SPL_I2C=y
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CONFIG_SPL_POWER=y
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CONFIG_SPL_WATCHDOG=y
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CONFIG_SYS_PROMPT="u-boot=> "
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CONFIG_SYS_MAXARGS=64
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CONFIG_SYS_CBSIZE=2048
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CONFIG_SYS_PBSIZE=2074
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# CONFIG_CMD_EXPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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# CONFIG_CMD_CRC32 is not set
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CONFIG_CMD_CLK=y
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CONFIG_CMD_FUSE=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SYS_MMC_ENV_DEV=1
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CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_USE_ETHPRIME=y
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CONFIG_ETHPRIME="FEC"
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CONFIG_SPL_DM=y
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CONFIG_SPL_CLK_COMPOSITE_CCF=y
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CONFIG_CLK_COMPOSITE_CCF=y
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CONFIG_SPL_CLK_IMX8MM=y
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CONFIG_CLK_IMX8MM=y
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CONFIG_MXC_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_MMC_IO_VOLTAGE=y
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CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS400_ES_SUPPORT=y
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_FSL_USDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_PINCTRL_IMX8M=y
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CONFIG_DM_PMIC=y
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CONFIG_SPL_DM_PMIC_PCA9450=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_PWM=y
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CONFIG_PWM_IMX=y
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CONFIG_DM_SERIAL=y
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CONFIG_MXC_UART=y
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CONFIG_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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CONFIG_SYSRESET_PSCI=y
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CONFIG_SYSRESET_WATCHDOG=y
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CONFIG_DM_THERMAL=y
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CONFIG_IMX_WATCHDOG=y
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CONFIG_NXP_FSPI=y
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CONFIG_SPI=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SF_DEFAULT_BUS=0
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CONFIG_SF_DEFAULT_CS=0
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CONFIG_SF_DEFAULT_SPEED=40000000
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_FSPI_CONF_HEADER=y
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CONFIG_FSPI_CONF_FILE="fspi_header.bin"
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CONFIG_READ_CLK_SOURCE=0x00
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CONFIG_DEVICE_TYPE=0x01
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CONFIG_FLASH_PAD_TYPE=0x01
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CONFIG_SERIAL_CLK_FREQUENCY=0x02
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CONFIG_LUT_CUSTOM_SEQUENCE=0x00
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CONFIG_LUT_SEQUENCE="0x0b, 0x04, 0x18, 0x08, 0x08, 0x30, 0x04, 0x24"
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