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64e7cdb5e8
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
214 lines
8.9 KiB
C
214 lines
8.9 KiB
C
/*
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* Based on Linux i.MX iomux-v3.h file:
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* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
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* <armlinux@phytec.de>
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*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __MACH_IOMUX_V3_H__
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#define __MACH_IOMUX_V3_H__
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/*
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* build IOMUX_PAD structure
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*
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* This iomux scheme is based around pads, which are the physical balls
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* on the processor.
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*
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* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
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* things like driving strength and pullup/pulldown.
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* - Each pad can have but not necessarily does have an output routing register
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* (IOMUXC_SW_MUX_CTL_PAD_x).
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* - Each pad can have but not necessarily does have an input routing register
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* (IOMUXC_x_SELECT_INPUT)
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*
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* The three register sets do not have a fixed offset to each other,
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* hence we order this table by pad control registers (which all pads
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* have) and put the optional i/o routing registers into additional
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* fields.
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*
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* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
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* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
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*
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* IOMUX/PAD Bit field definitions
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*
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* MUX_CTRL_OFS: 0..11 (12)
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* PAD_CTRL_OFS: 12..23 (12)
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* SEL_INPUT_OFS: 24..35 (12)
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* MUX_MODE + SION: 36..40 (5)
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* PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
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* SEL_INP: 59..62 (4)
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* reserved: 63 (1)
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*/
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typedef u64 iomux_v3_cfg_t;
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#define MUX_CTRL_OFS_SHIFT 0
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#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
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#define MUX_PAD_CTRL_OFS_SHIFT 12
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#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
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MUX_PAD_CTRL_OFS_SHIFT)
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#define MUX_SEL_INPUT_OFS_SHIFT 24
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#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
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MUX_SEL_INPUT_OFS_SHIFT)
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#define MUX_MODE_SHIFT 36
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#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
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#define MUX_PAD_CTRL_SHIFT 41
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#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
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#define MUX_SEL_INPUT_SHIFT 59
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#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
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#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
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#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
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sel_input, pad_ctrl) \
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(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
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((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
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((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
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((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
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((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
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((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
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#define NO_PAD_CTRL (1 << 17)
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#define GPIO_PIN_MASK 0x1f
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#define GPIO_PORT_SHIFT 5
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#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
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#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
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#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
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#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
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#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
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#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
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#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
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#define MUX_CONFIG_SION (0x1 << 4)
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int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
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int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
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/*
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* IOMUXC_GPR13 bit fields
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*/
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#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30)
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#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29)
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#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28)
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#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27)
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#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24)
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#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19)
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#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16
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#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
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#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15)
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#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14)
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#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11)
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#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7)
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#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
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#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
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#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24)
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#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24)
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#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24)
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#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24)
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#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24)
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#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24)
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#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24)
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#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24)
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#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
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#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
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#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
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#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
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#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
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#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
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#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15)
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#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15)
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#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14)
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#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14)
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#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11)
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#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11)
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#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11)
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#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11)
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#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11)
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#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7)
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#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2)
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#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2)
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#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
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#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
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#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2
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#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
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|IOMUXC_GPR13_SATA_PHY_7_MASK \
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|IOMUXC_GPR13_SATA_PHY_6_MASK \
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|IOMUXC_GPR13_SATA_SPEED_MASK \
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|IOMUXC_GPR13_SATA_PHY_5_MASK \
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|IOMUXC_GPR13_SATA_PHY_4_MASK \
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|IOMUXC_GPR13_SATA_PHY_3_MASK \
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|IOMUXC_GPR13_SATA_PHY_2_MASK \
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|IOMUXC_GPR13_SATA_PHY_1_MASK)
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#endif /* __MACH_IOMUX_V3_H__*/
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