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https://github.com/AsahiLinux/u-boot
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1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
262 lines
5.6 KiB
C
262 lines
5.6 KiB
C
/*
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* Taken from the linux kernel file of the same name
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*
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* (C) Copyright 2012
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_X86_MSR_H
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#define _ASM_X86_MSR_H
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#include <asm/msr-index.h>
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/ioctl.h>
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#define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8])
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#define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8])
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#ifdef __KERNEL__
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#include <linux/errno.h>
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struct msr {
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union {
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struct {
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u32 l;
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u32 h;
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};
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u64 q;
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};
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};
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struct msr_info {
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u32 msr_no;
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struct msr reg;
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struct msr *msrs;
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int err;
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};
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struct msr_regs_info {
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u32 *regs;
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int err;
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};
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static inline unsigned long long native_read_tscp(unsigned int *aux)
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{
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unsigned long low, high;
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asm volatile(".byte 0x0f,0x01,0xf9"
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: "=a" (low), "=d" (high), "=c" (*aux));
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return low | ((u64)high << 32);
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}
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/*
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* both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
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* constraint has different meanings. For i386, "A" means exactly
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* edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
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* it means rax *or* rdx.
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*/
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#ifdef CONFIG_X86_64
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#define DECLARE_ARGS(val, low, high) unsigned low, high
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#define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32))
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#define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
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#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
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#else
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#define DECLARE_ARGS(val, low, high) unsigned long long val
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#define EAX_EDX_VAL(val, low, high) (val)
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#define EAX_EDX_ARGS(val, low, high) "A" (val)
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#define EAX_EDX_RET(val, low, high) "=A" (val)
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#endif
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static inline __attribute__((no_instrument_function))
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unsigned long long native_read_msr(unsigned int msr)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
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return EAX_EDX_VAL(val, low, high);
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}
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static inline void native_write_msr(unsigned int msr,
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unsigned low, unsigned high)
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{
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asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
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}
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extern unsigned long long native_read_tsc(void);
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extern int native_rdmsr_safe_regs(u32 regs[8]);
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extern int native_wrmsr_safe_regs(u32 regs[8]);
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static inline unsigned long long native_read_pmc(int counter)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
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return EAX_EDX_VAL(val, low, high);
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#include <errno.h>
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/*
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* Access to machine-specific registers (available on 586 and better only)
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* Note: the rd* operations modify the parameters directly (without using
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* pointer indirection), this allows gcc to optimize better
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*/
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#define rdmsr(msr, val1, val2) \
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do { \
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u64 __val = native_read_msr((msr)); \
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(void)((val1) = (u32)__val); \
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(void)((val2) = (u32)(__val >> 32)); \
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} while (0)
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static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
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{
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native_write_msr(msr, low, high);
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}
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#define rdmsrl(msr, val) \
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((val) = native_read_msr((msr)))
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#define wrmsrl(msr, val) \
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native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
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static inline void msr_clrsetbits_64(unsigned msr, u64 clear, u64 set)
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{
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u64 val;
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val = native_read_msr(msr);
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val &= ~clear;
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val |= set;
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wrmsrl(msr, val);
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}
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static inline void msr_setbits_64(unsigned msr, u64 set)
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{
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u64 val;
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val = native_read_msr(msr);
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val |= set;
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wrmsrl(msr, val);
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}
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static inline void msr_clrbits_64(unsigned msr, u64 clear)
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{
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u64 val;
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val = native_read_msr(msr);
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val &= ~clear;
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wrmsrl(msr, val);
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}
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/* rdmsr with exception handling */
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#define rdmsr_safe(msr, p1, p2) \
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({ \
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int __err; \
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u64 __val = native_read_msr_safe((msr), &__err); \
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(*p1) = (u32)__val; \
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(*p2) = (u32)(__val >> 32); \
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__err; \
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})
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static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
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{
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u32 gprs[8] = { 0 };
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int err;
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gprs[1] = msr;
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gprs[7] = 0x9c5a203a;
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err = native_rdmsr_safe_regs(gprs);
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*p = gprs[0] | ((u64)gprs[2] << 32);
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return err;
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}
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static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
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{
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u32 gprs[8] = { 0 };
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gprs[0] = (u32)val;
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gprs[1] = msr;
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gprs[2] = val >> 32;
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gprs[7] = 0x9c5a203a;
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return native_wrmsr_safe_regs(gprs);
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}
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static inline int rdmsr_safe_regs(u32 regs[8])
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{
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return native_rdmsr_safe_regs(regs);
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}
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static inline int wrmsr_safe_regs(u32 regs[8])
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{
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return native_wrmsr_safe_regs(regs);
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}
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typedef struct msr_t {
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uint32_t lo;
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uint32_t hi;
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} msr_t;
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static inline struct msr_t msr_read(unsigned msr_num)
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{
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struct msr_t msr;
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rdmsr(msr_num, msr.lo, msr.hi);
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return msr;
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}
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static inline void msr_write(unsigned msr_num, msr_t msr)
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{
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wrmsr(msr_num, msr.lo, msr.hi);
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}
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#define rdtscl(low) \
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((low) = (u32)__native_read_tsc())
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#define rdtscll(val) \
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((val) = __native_read_tsc())
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#define rdpmc(counter, low, high) \
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do { \
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u64 _l = native_read_pmc((counter)); \
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(low) = (u32)_l; \
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(high) = (u32)(_l >> 32); \
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} while (0)
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#define rdtscp(low, high, aux) \
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do { \
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unsigned long long _val = native_read_tscp(&(aux)); \
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(low) = (u32)_val; \
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(high) = (u32)(_val >> 32); \
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} while (0)
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#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
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#endif /* !CONFIG_PARAVIRT */
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#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \
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(u32)((val) >> 32))
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#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
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#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
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struct msr *msrs_alloc(void);
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void msrs_free(struct msr *msrs);
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_X86_MSR_H */
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