mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 11:13:07 +00:00
5c86a8f7a1
This is supposed to be a build-system flag. Move it there so we can define it before linux/kconfig.h is included. Signed-off-by: Simon Glass <sjg@chromium.org>
122 lines
2.9 KiB
INI
122 lines
2.9 KiB
INI
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (C) 2017 PHYTEC America, LLC
|
|
*
|
|
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
|
|
* and create imximage boot image
|
|
*
|
|
* The syntax is taken as close as possible with the kwbimage
|
|
*/
|
|
|
|
#include <config.h>
|
|
|
|
IMAGE_VERSION 2
|
|
#ifdef CONFIG_IMX_HAB
|
|
CSF CONFIG_CSF_SIZE
|
|
#endif
|
|
|
|
BOOT_FROM sd
|
|
|
|
/*
|
|
* Device Configuration Data (DCD)
|
|
*
|
|
* Each entry must have the format:
|
|
* Addr-type Address Value
|
|
*
|
|
* where:
|
|
* Addr-type register length (1,2 or 4 bytes)
|
|
* Address absolute address of the register
|
|
* value value to be stored in the register
|
|
*/
|
|
|
|
/*
|
|
* Device Configuration Data (DCD)
|
|
*
|
|
* Each entry must have the format:
|
|
* Addr-type Address Value
|
|
*
|
|
* where:
|
|
* Addr-type register length (1,2 or 4 bytes)
|
|
* Address absolute address of the register
|
|
* value value to be stored in the register
|
|
*/
|
|
|
|
/* DDR initialization came from Phytec */
|
|
DATA 4 0x30340004 0x4F400005
|
|
/* Clear then set bit30 to ensure exit from DDR retention */
|
|
DATA 4 0x30360388 0x40000000
|
|
DATA 4 0x30360384 0x40000000
|
|
|
|
/* deassert presetn */
|
|
DATA 4 0x30391000 0x00000002
|
|
|
|
/* DDR Controller Regs */
|
|
DATA 4 0x307a0000 0x01040001
|
|
DATA 4 0x307a0064 0x00400046
|
|
DATA 4 0x307a0490 0x00000001
|
|
DATA 4 0x307a00d4 0x00690000
|
|
DATA 4 0x307a00d0 0x00020083
|
|
DATA 4 0x307a00dc 0x09300004
|
|
DATA 4 0x307a00e0 0x04480000
|
|
DATA 4 0x307a00e4 0x00100004
|
|
DATA 4 0x307a00f4 0x0000033f
|
|
DATA 4 0x307a0100 0x090e110a
|
|
DATA 4 0x307a0104 0x0007020e
|
|
DATA 4 0x307a0108 0x03040407
|
|
DATA 4 0x307a010c 0x00002006
|
|
DATA 4 0x307a0110 0x04020304
|
|
DATA 4 0x307a0114 0x03030202
|
|
DATA 4 0x307a0120 0x00000803
|
|
DATA 4 0x307a0180 0x00800020
|
|
DATA 4 0x307a0190 0x02098204
|
|
DATA 4 0x307a0194 0x00030303
|
|
DATA 4 0x307a01a0 0x80400003
|
|
DATA 4 0x307a01a4 0x00100020
|
|
DATA 4 0x307a01a8 0x80100004
|
|
DATA 4 0x307a0200 0x0000001f
|
|
DATA 4 0x307a0204 0x00080808
|
|
DATA 4 0x307a020c 0x00000000
|
|
DATA 4 0x307a0210 0x00000f0f
|
|
DATA 4 0x307a0214 0x07070707
|
|
DATA 4 0x307a0218 0x0f070707
|
|
DATA 4 0x307a0240 0x06000604
|
|
DATA 4 0x307a0244 0x00000001
|
|
|
|
/* deassert presetn */
|
|
DATA 4 0x30391000 0x00000000
|
|
|
|
/* PHY Controller Regs */
|
|
DATA 4 0x30790000 0x17420f40
|
|
DATA 4 0x30790004 0x10210100
|
|
DATA 4 0x30790010 0x00060807
|
|
DATA 4 0x307900b0 0x1010007e
|
|
DATA 4 0x3079009c 0x00000d6e
|
|
/* write leveling values for each byte lane */
|
|
DATA 4 0x3079006c 0x06090108
|
|
/* write leveling resync cycle */
|
|
DATA 4 0x30790078 0x00000001
|
|
DATA 4 0x30790078 0x00000000
|
|
DATA 4 0x30790030 0x08080808
|
|
DATA 4 0x30790020 0x08080808
|
|
DATA 4 0x30790050 0x01000010
|
|
DATA 4 0x30790050 0x00000010
|
|
DATA 4 0x30790018 0x0000000f
|
|
|
|
/* start manual ZQ */
|
|
DATA 4 0x307900c0 0x0e407304
|
|
DATA 4 0x307900c0 0x0e447304
|
|
DATA 4 0x307900c0 0x0e447306
|
|
DATA 4 0x307900c0 0x0e447304
|
|
|
|
CHECK_BITS_SET 4 0x307900c4 0x1
|
|
|
|
/* end manual ZQ */
|
|
DATA 4 0x307900c0 0x0e407304
|
|
|
|
/* final init sequence */
|
|
DATA 4 0x30384130 0x00000000
|
|
DATA 4 0x30340020 0x00000178
|
|
DATA 4 0x30384130 0x00000002
|
|
DATA 4 0x30790018 0x0000000f
|
|
|
|
CHECK_BITS_SET 4 0x307a0004 0x1
|