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caf2233b28
The bcm283x family of SoCs have a GPIO controller that also acts as pinctrl controller. This patch introduces a new pinctrl driver that can actually properly mux devices into their device tree defined pin states and is now the primary owner of the gpio device. The previous GPIO driver gets moved into a subdevice of the pinctrl driver, bound to the same OF node. That way whenever a device asks for pinctrl support, it gets it automatically from the pinctrl driver and GPIO support is still available in the normal command line phase. Signed-off-by: Alexander Graf <agraf@suse.de>
64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
/*
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* Copyright (C) 2012 Vikram Narayananan
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* <vikram186@gmail.com>
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* (C) Copyright 2012,2015 Stephen Warren
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _BCM2835_GPIO_H_
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#define _BCM2835_GPIO_H_
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#define BCM2835_GPIO_COUNT 54
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#define BCM2835_GPIO_FSEL_MASK 0x7
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#define BCM2835_GPIO_INPUT 0x0
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#define BCM2835_GPIO_OUTPUT 0x1
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#define BCM2835_GPIO_ALT0 0x4
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#define BCM2835_GPIO_ALT1 0x5
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#define BCM2835_GPIO_ALT2 0x6
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#define BCM2835_GPIO_ALT3 0x7
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#define BCM2835_GPIO_ALT4 0x3
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#define BCM2835_GPIO_ALT5 0x2
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#define BCM2835_GPIO_COMMON_BANK(gpio) ((gpio < 32) ? 0 : 1)
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#define BCM2835_GPIO_COMMON_SHIFT(gpio) (gpio & 0x1f)
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#define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10)
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#define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3)
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struct bcm2835_gpio_regs {
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u32 gpfsel[6];
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u32 reserved1;
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u32 gpset[2];
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u32 reserved2;
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u32 gpclr[2];
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u32 reserved3;
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u32 gplev[2];
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u32 reserved4;
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u32 gpeds[2];
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u32 reserved5;
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u32 gpren[2];
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u32 reserved6;
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u32 gpfen[2];
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u32 reserved7;
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u32 gphen[2];
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u32 reserved8;
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u32 gplen[2];
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u32 reserved9;
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u32 gparen[2];
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u32 reserved10;
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u32 gppud;
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u32 gppudclk[2];
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};
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/**
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* struct bcm2835_gpio_platdata - GPIO platform description
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*
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* @base: Base address of GPIO controller
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*/
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struct bcm2835_gpio_platdata {
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unsigned long base;
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};
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#endif /* _BCM2835_GPIO_H_ */
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