mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-28 05:53:54 +00:00
171 lines
4.2 KiB
C
171 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
|
|
* Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
|
|
* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <spl.h>
|
|
|
|
#include <asm/io.h>
|
|
#include <linux/sizes.h>
|
|
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/crm_regs.h>
|
|
#include <asm/arch/iomux.h>
|
|
#include <asm/arch/mx6-ddr.h>
|
|
#include <asm/arch/mx6-pins.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define IMX6SDL_DRIVE_STRENGTH 0x28
|
|
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
|
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
|
|
|
static iomux_v3_cfg_t const uart3_pads[] = {
|
|
IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
|
};
|
|
|
|
#ifdef CONFIG_SPL_OS_BOOT
|
|
int spl_start_uboot(void)
|
|
{
|
|
/* break into full u-boot on 'c' */
|
|
if (serial_tstc() && serial_getc() == 'c')
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
|
|
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_cas = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_ras = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_reset = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdba2 = 0x00000000,
|
|
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
|
|
};
|
|
|
|
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
|
|
.grp_ddr_type = 0x000c0000,
|
|
.grp_ddrmode_ctl = 0x00020000,
|
|
.grp_ddrpke = 0x00000000,
|
|
.grp_addds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_ddrmode = 0x00020000,
|
|
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
|
|
};
|
|
|
|
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
|
|
.mem_speed = 1600,
|
|
.density = 4,
|
|
.width = 32,
|
|
.banks = 8,
|
|
.rowaddr = 14,
|
|
.coladdr = 10,
|
|
.pagesz = 2,
|
|
.trcd = 1375,
|
|
.trcmin = 4875,
|
|
.trasmin = 3500,
|
|
.SRT = 0,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
|
|
.p0_mpwldectrl0 = 0x0042004b,
|
|
.p0_mpwldectrl1 = 0x0038003c,
|
|
.p0_mpdgctrl0 = 0x42340230,
|
|
.p0_mpdgctrl1 = 0x0228022c,
|
|
.p0_mprddlctl = 0x42444646,
|
|
.p0_mpwrdlctl = 0x38382e2e,
|
|
};
|
|
|
|
static struct mx6_ddr_sysinfo mem_dl = {
|
|
.dsize = 1,
|
|
.cs1_mirror = 0,
|
|
/* config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32,
|
|
.ncs = 1,
|
|
.bi_on = 1,
|
|
.rtt_nom = 1,
|
|
.rtt_wr = 1,
|
|
.ralat = 5,
|
|
.walat = 0,
|
|
.mif3_mode = 3,
|
|
.rst_to_cke = 0x23,
|
|
.sde_to_rst = 0x10,
|
|
.refsel = 1,
|
|
.refr = 7,
|
|
};
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
|
|
|
|
udelay(100);
|
|
}
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
writel(0x00003f3f, &ccm->CCGR0);
|
|
writel(0x0030fc00, &ccm->CCGR1);
|
|
writel(0x000fc000, &ccm->CCGR2);
|
|
writel(0x3f300000, &ccm->CCGR3);
|
|
writel(0xff00f300, &ccm->CCGR4);
|
|
writel(0x0f0000c3, &ccm->CCGR5);
|
|
writel(0x000003cc, &ccm->CCGR6);
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
ccgr_init();
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
gpr_init();
|
|
|
|
/* iomux */
|
|
SETUP_IOMUX_PADS(uart3_pads);
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
}
|