mirror of
https://github.com/AsahiLinux/u-boot
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6e7df1d151
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010, 2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _WARMBOOT_AVP_H_
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#define _WARMBOOT_AVP_H_
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#define TEGRA_DEV_L 0
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#define TEGRA_DEV_H 1
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#define TEGRA_DEV_U 2
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#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
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#define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE)
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#define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0)
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#define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4)
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#define USEC_CFG_DIVISOR_MASK 0xffff
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#define CFG_CTL_TBE (1 << 7)
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#define CFG_CTL_JTAG (1 << 6)
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#define CPU_RST (1 << 0)
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#define CLK_ENB_CPU (1 << 0)
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#define SWR_TRIG_SYS_RST (1 << 2)
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#define SWR_CSITE_RST (1 << 9)
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#define PWRGATE_STATUS_CPU (1 << 0)
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#define PWRGATE_TOGGLE_PARTID_CPU (0 << 0)
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#define PWRGATE_TOGGLE_START (1 << 8)
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#define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 (3 << 0)
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#define CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8)
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#define CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8)
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#define CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9)
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#define CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9)
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#define CPU_CMPLX_CPURESET0 (1 << 0)
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#define CPU_CMPLX_CPURESET1 (1 << 1)
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#define CPU_CMPLX_DERESET0 (1 << 4)
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#define CPU_CMPLX_DERESET1 (1 << 5)
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#define CPU_CMPLX_DBGRESET0 (1 << 12)
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#define CPU_CMPLX_DBGRESET1 (1 << 13)
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#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0)
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#define PLLM_OUT1_CLKEN_ENABLE (1 << 1)
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#define PLLM_OUT1_RATIO_VAL_8 (8 << 8)
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#define SCLK_SYS_STATE_IDLE (1 << 28)
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#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
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#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
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#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
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#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
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#define EVENT_ZERO_VAL_20 (20 << 0)
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#define EVENT_MSEC (1 << 24)
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#define EVENT_JTAG (1 << 28)
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#define EVENT_MODE_STOP (2 << 29)
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#define CCLK_PLLP_BURST_POLICY 0x20004444
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#endif
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