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c0d7f1fbad
This patch solves the following warnings: drivers/adc/stm32-adc-core.c: In function 'stm32h7_adc_clk_sel': warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { ^ warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { ^ Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com>
210 lines
5 KiB
C
210 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>
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*
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* Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <power/regulator.h>
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#include "stm32-adc-core.h"
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/* STM32H7 - common registers for all ADC instances */
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#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
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/* STM32H7_ADC_CCR - bit fields */
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#define STM32H7_PRESC_SHIFT 18
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#define STM32H7_PRESC_MASK GENMASK(21, 18)
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#define STM32H7_CKMODE_SHIFT 16
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#define STM32H7_CKMODE_MASK GENMASK(17, 16)
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/* STM32 H7 maximum analog clock rate (from datasheet) */
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#define STM32H7_ADC_MAX_CLK_RATE 36000000
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/**
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* struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
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* @ckmode: ADC clock mode, Async or sync with prescaler.
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* @presc: prescaler bitfield for async clock mode
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* @div: prescaler division ratio
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*/
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struct stm32h7_adc_ck_spec {
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u32 ckmode;
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u32 presc;
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int div;
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};
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static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
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/* 00: CK_ADC[1..3]: Asynchronous clock modes */
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{ 0, 0, 1 },
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{ 0, 1, 2 },
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{ 0, 2, 4 },
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{ 0, 3, 6 },
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{ 0, 4, 8 },
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{ 0, 5, 10 },
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{ 0, 6, 12 },
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{ 0, 7, 16 },
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{ 0, 8, 32 },
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{ 0, 9, 64 },
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{ 0, 10, 128 },
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{ 0, 11, 256 },
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/* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
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{ 1, 0, 1 },
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{ 2, 0, 2 },
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{ 3, 0, 4 },
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};
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static int stm32h7_adc_clk_sel(struct udevice *dev,
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struct stm32_adc_common *common)
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{
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u32 ckmode, presc;
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unsigned long rate;
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unsigned int i;
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int div;
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/* stm32h7 bus clock is common for all ADC instances (mandatory) */
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if (!clk_valid(&common->bclk)) {
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dev_err(dev, "No bclk clock found\n");
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return -ENOENT;
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}
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/*
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* stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
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* So, choice is to have bus clock mandatory and adc clock optional.
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* If optional 'adc' clock has been found, then try to use it first.
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*/
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if (clk_valid(&common->aclk)) {
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/*
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* Asynchronous clock modes (e.g. ckmode == 0)
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* From spec: PLL output musn't exceed max rate
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*/
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rate = clk_get_rate(&common->aclk);
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if (!rate) {
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dev_err(dev, "Invalid aclk rate: 0\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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presc = stm32h7_adc_ckmodes_spec[i].presc;
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div = stm32h7_adc_ckmodes_spec[i].div;
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if (ckmode)
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continue;
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if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
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goto out;
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}
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}
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/* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
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rate = clk_get_rate(&common->bclk);
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if (!rate) {
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dev_err(dev, "Invalid bus clock rate: 0\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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presc = stm32h7_adc_ckmodes_spec[i].presc;
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div = stm32h7_adc_ckmodes_spec[i].div;
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if (!ckmode)
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continue;
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if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
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goto out;
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}
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dev_err(dev, "clk selection failed\n");
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return -EINVAL;
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out:
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/* rate used later by each ADC instance to control BOOST mode */
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common->rate = rate / div;
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/* Set common clock mode and prescaler */
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clrsetbits_le32(common->base + STM32H7_ADC_CCR,
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STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK,
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ckmode << STM32H7_CKMODE_SHIFT |
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presc << STM32H7_PRESC_SHIFT);
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dev_dbg(dev, "Using %s clock/%d source at %ld kHz\n",
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ckmode ? "bus" : "adc", div, common->rate / 1000);
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return 0;
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}
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static int stm32_adc_core_probe(struct udevice *dev)
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{
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struct stm32_adc_common *common = dev_get_priv(dev);
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int ret;
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common->base = dev_read_addr_ptr(dev);
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if (!common->base) {
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dev_err(dev, "can't get address\n");
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return -ENOENT;
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}
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ret = device_get_supply_regulator(dev, "vref-supply", &common->vref);
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if (ret) {
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dev_err(dev, "can't get vref-supply: %d\n", ret);
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return ret;
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}
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ret = regulator_get_value(common->vref);
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if (ret < 0) {
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dev_err(dev, "can't get vref-supply value: %d\n", ret);
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return ret;
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}
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common->vref_uv = ret;
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ret = clk_get_by_name(dev, "adc", &common->aclk);
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if (!ret) {
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ret = clk_enable(&common->aclk);
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if (ret) {
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dev_err(dev, "Can't enable aclk: %d\n", ret);
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return ret;
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}
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}
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ret = clk_get_by_name(dev, "bus", &common->bclk);
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if (!ret) {
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ret = clk_enable(&common->bclk);
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if (ret) {
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dev_err(dev, "Can't enable bclk: %d\n", ret);
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goto err_aclk_disable;
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}
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}
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ret = stm32h7_adc_clk_sel(dev, common);
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if (ret)
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goto err_bclk_disable;
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return ret;
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err_bclk_disable:
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if (clk_valid(&common->bclk))
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clk_disable(&common->bclk);
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err_aclk_disable:
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if (clk_valid(&common->aclk))
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clk_disable(&common->aclk);
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return ret;
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}
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static const struct udevice_id stm32_adc_core_ids[] = {
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{ .compatible = "st,stm32h7-adc-core" },
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{ .compatible = "st,stm32mp1-adc-core" },
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{}
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};
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U_BOOT_DRIVER(stm32_adc_core) = {
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.name = "stm32-adc-core",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = stm32_adc_core_ids,
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.probe = stm32_adc_core_probe,
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.priv_auto_alloc_size = sizeof(struct stm32_adc_common),
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};
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