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u-boot/arch/riscv/cpu
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Chanho Park 1c55d62fb9 riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback 
Since the Patch 55171aedda, VisionFive2 booting has been broken [1].
VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting went
to panic from initr_dm_devices due to lack of a timer device.

- Error logs
initcall sequence 00000000fffd8d38 failed at call 00000000402185e4
(err=-19)

Thus, we need to move riscv_cpu_probe function in order to register
the timer earlier than initr_dm_devices.

Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
2023-08-22 08:07:54 -06:00
..
andesv5 riscv: Rename Andes cpu and board names 2023-02-17 19:07:48 +08:00
fu540 common: return type board_get_usable_ram_top 2023-08-15 18:21:17 +02:00
fu740 common: return type board_get_usable_ram_top 2023-08-15 18:21:17 +02:00
generic common: return type board_get_usable_ram_top 2023-08-15 18:21:17 +02:00
jh7110 common: return type board_get_usable_ram_top 2023-08-15 18:21:17 +02:00
cpu.c riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback 2023-08-22 08:07:54 -06:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
start.S riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation 2023-08-10 10:58:12 +08:00
u-boot-spl.lds riscv: Update alignment for some sections in linker scripts 2023-04-20 20:45:08 +08:00
u-boot.lds riscv: Fix alignment of RELA sections in the linker scripts 2023-06-27 10:09:51 +08:00