mirror of
https://github.com/AsahiLinux/u-boot
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96e21f86e8
All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
381 lines
15 KiB
C
381 lines
15 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* zeus.h - configuration for Zeus board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_ZEUS 1 /* Board is Zeus */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_405EP 1 /* Specifc 405EP support*/
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
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#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0x01 /* PHY address */
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#define CONFIG_HAS_ETH1 1
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#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_PHY_RESET 1
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#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_LOG
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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/* POST support */
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
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CONFIG_SYS_POST_CPU | \
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CONFIG_SYS_POST_CACHE | \
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CONFIG_SYS_POST_UART | \
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CONFIG_SYS_POST_ETHER)
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#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
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/* Define here the base-addresses of the UARTs to test in POST */
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#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
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#define CONFIG_LOGBUFFER
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#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*-----------------------------------------------------------------------
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* SDRAM
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*----------------------------------------------------------------------*/
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/*
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* SDRAM configuration (please see cpu/ppc/sdram.[ch])
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*/
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
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/* SDRAM timings used in datasheet */
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#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
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#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
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#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
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#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
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#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
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#define CONFIG_SYS_BASE_BAUD 691200
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/* these are for the ST M24C02 2kbit serial i2c eeprom */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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/*
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* The layout of the I2C EEPROM, used for bootstrap setup and for board-
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* specific values, like ethaddr... that can be restored via the sw-reset
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* button
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*/
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#define FACTORY_RESET_I2C_EEPROM 0x50
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#define FACTORY_RESET_ENV_OFFS 0x80
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#define FACTORY_RESET_ENV_SIZE 0x80
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory (OCM) for temperary stack until sdram is tested */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
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#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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/* reserve some memory for POST and BOOT limit info */
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
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/* extra data in OCM */
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#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
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#define CONFIG_SYS_POST_MAGIC (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
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#define CONFIG_SYS_POST_VAL (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (Flash 16M) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x05815600
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#define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
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/*-----------------------------------------------------------------------
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* Definitions for GPIO setup (PPC405EP specific)
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*
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* GPIO0[0] - External Bus Controller BLAST output
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* GPIO0[1-9] - Instruction trace outputs
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* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
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* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
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* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
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* GPIO0[24-27] - UART0 control signal inputs/outputs
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* GPIO0[28-29] - UART1 data signal input/output
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* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
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*/
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#define CONFIG_SYS_GPIO0_OSRH 0x15555550 /* Chip selects */
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#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
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#define CONFIG_SYS_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
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#define CONFIG_SYS_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
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#define CONFIG_SYS_GPIO0_TSRH 0x00000000
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#define CONFIG_SYS_GPIO0_TSRL 0x00000000
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#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
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#define CONFIG_SYS_GPIO0_ODR 0x00000000
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#define CONFIG_SYS_GPIO_SW_RESET 1
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#define CONFIG_SYS_GPIO_ZEUS_PE 12
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#define CONFIG_SYS_GPIO_LED_RED 22
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#define CONFIG_SYS_GPIO_LED_GREEN 23
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/* Time in milli-seconds */
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#define CONFIG_SYS_TIME_POST 5000
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#define CONFIG_SYS_TIME_FACTORY_RESET 10000
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Pass open firmware flat tree
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*/
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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/* ENVIRONMENT VARS */
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#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
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#define CONFIG_IPADDR 192.168.1.10
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#define CONFIG_SERVERIP 192.168.1.100
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#define CONFIG_GATEWAYIP 192.168.1.100
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#define CONFIG_ETHADDR 50:00:00:00:06:00
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#define CONFIG_ETH1ADDR 50:00:00:00:06:01
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"logversion=2\0" \
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"hostname=zeus\0" \
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"netdev=eth0\0" \
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"ethact=ppc_4xx_eth0\0" \
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"netmask=255.255.255.0\0" \
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"ramdisk_size=50000\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw" \
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" nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw" \
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" ramdisk_size=${ramdisk_size}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0," \
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"${baudrate}\0" \
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"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
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"run nfsargs addip addtty;bootm\0" \
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"net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
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"tftp ${ramdisk_mem_addr} ${file_fs};" \
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"run ramargs addip addtty;" \
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"bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
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"rootpath=/target_fs/zeus\0" \
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"kernel_fl_addr=ff000000\0" \
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"kernel_mem_addr=200000\0" \
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"ramdisk_fl_addr=ff300000\0" \
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"ramdisk_mem_addr=4000000\0" \
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"uboot_fl_addr=fffc0000\0" \
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"uboot_mem_addr=100000\0" \
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"file_uboot=/zeus/u-boot.bin\0" \
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"tftp_uboot=tftp 100000 ${file_uboot}\0" \
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"update_uboot=protect off fffc0000 ffffffff;" \
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"era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
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"protect on fffc0000 ffffffff\0" \
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"upd_uboot=run tftp_uboot;run update_uboot\0" \
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"file_kernel=/zeus/uImage_ba\0" \
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"tftp_kernel=tftp 100000 ${file_kernel}\0" \
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"update_kernel=protect off ff000000 ff17ffff;" \
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"era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
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"upd_kernel=run tftp_kernel;run update_kernel\0" \
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"file_fs=/zeus/rootfs_ba.img\0" \
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"tftp_fs=tftp 100000 ${file_fs}\0" \
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"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
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"cp.b 100000 ff300000 580000\0" \
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"upd_fs=run tftp_fs;run update_fs\0" \
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"bootcmd=chkreset;run ramargs addip addtty addmisc;" \
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"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
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""
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#endif /* __CONFIG_H */
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