mirror of
https://github.com/AsahiLinux/u-boot
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afac8b0717
The SPI flash define is named CONFIG_SF_DEFAULT_SPEED, not CONFIG_SF_DEFAULT_HZ, so fix the typos in the Blackfin boards. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
152 lines
4 KiB
C
152 lines
4 KiB
C
/*
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* U-boot - Configuration file for BF538F EZ-Kit Lite board
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*/
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#ifndef __CONFIG_BF538F_EZKIT_H__
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#define __CONFIG_BF538F_EZKIT_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf538-0.4
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 25000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 21
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 4
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 10
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#define CONFIG_MEM_SIZE 64
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#define CONFIG_EBIU_SDRRC_VAL (0x03F6)
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#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)
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#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN)
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#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
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#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
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/*
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* Network Settings
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*/
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_DRIVER_SMC91111 1
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#define CONFIG_SMC91111_BASE 0x20310300
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#define CONFIG_HOSTNAME bf538f-ezkit
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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/*
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* Flash Settings
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 71
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_WINBOND
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/*
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* Env Storage Settings
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*/
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x4000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OFFSET 0x4000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#endif
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
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#define ENV_IS_EMBEDDED
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#else
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#define ENV_IS_EMBEDDED_CUSTOM
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#endif
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#ifdef ENV_IS_EMBEDDED
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/* WARNING - the following is hand-optimized to fit within
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* the sector before the environment sector. If it throws
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* an error during compilation remove an object here to get
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* it linked after the configuration sector.
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*/
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# define LDS_BOARD_TEXT \
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cpu/blackfin/traps.o (.text .text.*); \
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cpu/blackfin/interrupt.o (.text .text.*); \
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cpu/blackfin/serial.o (.text .text.*); \
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common/dlmalloc.o (.text .text.*); \
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lib_generic/crc32.o (.text .text.*); \
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. = DEFINED(env_offset) ? env_offset : .; \
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common/env_embedded.o (.text .text.*);
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#endif
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/*
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* I2C Settings
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*/
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#define CONFIG_BFIN_TWI_I2C 1
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0
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/*
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* Misc Settings
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*/
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 0
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif
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