mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
691d719db7
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
272 lines
6.9 KiB
C
272 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*
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* Portions taken from coreboot
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*/
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#include <common.h>
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#include <dm.h>
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#include <ec_commands.h>
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#include <init.h>
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#include <log.h>
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#include <spi_flash.h>
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#include <spl.h>
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#include <syscon.h>
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#include <acpi/acpi_s3.h>
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#include <asm/cpu.h>
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#include <asm/cpu_common.h>
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#include <asm/cpu_x86.h>
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#include <asm/fast_spi.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/pci.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/lpc.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/systemagent.h>
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#include <asm/arch/uart.h>
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#include <asm/fsp2/fsp_api.h>
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#include <linux/sizes.h>
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#include <power/acpi_pmc.h>
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/* Define this here to avoid referencing any drivers for the debug UART 1 */
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#define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
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static void pch_uart_init(void)
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{
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/*
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* Set up the pinmux so that the UART rx/tx signals are connected
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* outside the SoC.
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*
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* There are about 500 lines of code required to program the GPIO
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* configuration for the UARTs. But it boils down to four writes, and
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* for the debug UART we want the minimum possible amount of code before
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* the UART is running. So just add the magic writes here. See
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* apl_hostbridge_early_init_pinctrl() for the full horror.
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*/
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if (PCI_FUNC(PCH_DEV_UART) == 1) {
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writel(0x40000402, 0xd0c50650);
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writel(0x3c47, 0xd0c50654);
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writel(0x40000400, 0xd0c50658);
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writel(0x3c48, 0xd0c5065c);
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} else { /* UART2 */
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writel(0x40000402, 0xd0c50670);
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writel(0x3c4b, 0xd0c50674);
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writel(0x40000400, 0xd0c50678);
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writel(0x3c4c, 0xd0c5067c);
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}
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#ifdef CONFIG_DEBUG_UART
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apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
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#endif
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}
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static void p2sb_enable_bar(ulong bar)
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{
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/* Enable PCR Base address in PCH */
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pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
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PCI_SIZE_32);
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pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
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/* Enable P2SB MSE */
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pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
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PCI_SIZE_8);
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}
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/*
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* board_debug_uart_init() - Init the debug UART ready for use
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*
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* This is the minimum init needed to get the UART running. It avoids any
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* drivers or complex code, so that the UART is running as soon as possible.
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*/
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void board_debug_uart_init(void)
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{
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p2sb_enable_bar(IOMAP_P2SB_BAR);
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pch_uart_init();
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}
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static int fast_spi_cache_bios_region(void)
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{
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uint map_size, offset;
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ulong map_base, base;
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int ret;
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ret = fast_spi_early_init(PCH_DEV_SPI, IOMAP_SPI_BASE);
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if (ret)
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return log_msg_ret("early_init", ret);
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ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
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&offset);
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if (ret)
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return log_msg_ret("get_mmap", ret);
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base = SZ_4G - map_size;
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mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
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log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
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return 0;
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}
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static void enable_pm_timer_emulation(struct udevice *pmc)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc);
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msr_t msr;
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/*
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* The derived frequency is calculated as follows:
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* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
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*
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* Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
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* used.
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*/
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msr.hi = (3579545ULL << 32) / CTC_FREQ;
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/* Set PM1 timer IO port and enable */
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msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
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debug("PM timer %x %x\n", msr.hi, msr.lo);
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msr_write(MSR_EMULATE_PM_TIMER, msr);
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}
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static void google_chromeec_ioport_range(uint *out_basep, uint *out_sizep)
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{
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uint base;
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uint size;
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if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
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base = MEC_EMI_BASE;
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size = MEC_EMI_SIZE;
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} else {
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base = EC_HOST_CMD_REGION0;
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size = 2 * EC_HOST_CMD_REGION_SIZE;
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/* Make sure MEMMAP region follows host cmd region */
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assert(base + size == EC_LPC_ADDR_MEMMAP);
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size += EC_MEMMAP_SIZE;
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}
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*out_basep = base;
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*out_sizep = size;
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}
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static void early_ec_init(void)
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{
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uint base, size;
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/*
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* Set up LPC decoding for the Chrome OS EC I/O port ranges:
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* - Ports 62/66, 60/64, and 200->208
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* - Chrome OS EC communication I/O ports
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*/
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lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 |
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LPC_IOE_LGE_200);
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google_chromeec_ioport_range(&base, &size);
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lpc_open_pmio_window(base, size);
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}
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static int arch_cpu_init_tpl(void)
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{
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struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc;
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int ret;
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ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
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if (ret)
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return log_msg_ret("PMC", ret);
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/* Clear global reset promotion bit */
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ret = pmc_global_reset_set_enable(pmc, false);
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if (ret)
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return log_msg_ret("disable global reset", ret);
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enable_pm_timer_emulation(pmc);
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ret = uclass_first_device_err(UCLASS_P2SB, &p2sb);
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if (ret)
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return log_msg_ret("p2sb", ret);
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ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa);
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if (ret)
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return log_msg_ret("northbridge", ret);
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gd->baudrate = CONFIG_BAUDRATE;
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ret = uclass_first_device_err(UCLASS_SERIAL, &serial);
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if (ret)
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return log_msg_ret("serial", ret);
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if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
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ret = uclass_first_device_err(UCLASS_SPI, &spi);
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if (ret)
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return log_msg_ret("SPI", ret);
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} else {
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/* Alternative code if we don't have SPI in TPL */
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if (IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH))
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printf("Warning: Enable APL_SPI_FLASHBOOT to use SPI-flash driver in TPL");
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ret = fast_spi_cache_bios_region();
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if (ret)
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return log_msg_ret("BIOS cache", ret);
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}
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ret = pmc_disable_tco(pmc);
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if (ret)
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return log_msg_ret("disable TCO", ret);
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ret = pmc_gpe_init(pmc);
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if (ret)
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return log_msg_ret("pmc_gpe", ret);
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ret = uclass_first_device_err(UCLASS_LPC, &lpc);
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if (ret)
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return log_msg_ret("lpc", ret);
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early_ec_init();
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return 0;
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}
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/*
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* Enables several BARs and devices which are needed for memory init
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* - MCH_BASE_ADDR is needed in order to talk to the memory controller
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* - HPET is enabled because FSP wants to store a pointer to global data in the
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* HPET comparator register
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*/
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static int arch_cpu_init_spl(void)
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{
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struct udevice *pmc, *p2sb;
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int ret;
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ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
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if (ret)
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return log_msg_ret("Could not probe PMC", ret);
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ret = uclass_first_device_err(UCLASS_P2SB, &p2sb);
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if (ret)
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return log_msg_ret("Cannot set up p2sb", ret);
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lpc_io_setup_comm_a_b();
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/* TODO(sjg@chromium.org): Enable upper RTC bank here */
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ret = pmc_init(pmc);
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if (ret < 0)
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return log_msg_ret("Could not init PMC", ret);
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#ifdef CONFIG_HAVE_ACPI_RESUME
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ret = pmc_prev_sleep_state(pmc);
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if (ret < 0)
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return log_msg_ret("Could not get PMC sleep state", ret);
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gd->arch.prev_sleep_state = ret;
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#endif
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return 0;
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}
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int arch_cpu_init(void)
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{
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int ret = 0;
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if (spl_phase() == PHASE_TPL)
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ret = arch_cpu_init_tpl();
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else if (spl_phase() == PHASE_SPL)
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ret = arch_cpu_init_spl();
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if (ret)
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printf("%s: Error %d\n", __func__, ret);
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return ret;
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}
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