mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 22:24:32 +00:00
84 lines
1.7 KiB
C
84 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Google, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/wdt.h>
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#include <linux/err.h>
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#include <dm/uclass.h>
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/*
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* Second Watchdog Timer by default is configured
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* to trigger secondary boot source.
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*/
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#define AST_2ND_BOOT_WDT 1
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/*
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* Third Watchdog Timer by default is configured
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* to toggle Flash address mode switch before reset.
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*/
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#define AST_FLASH_ADDR_DETECT_WDT 2
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DECLARE_GLOBAL_DATA_PTR;
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void lowlevel_init(void)
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{
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/*
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* These two watchdogs need to be stopped as soon as possible,
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* otherwise the board might hang. By default they are set to
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* a very short timeout and even simple debug write to serial
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* console early in the init process might cause them to fire.
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*/
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struct ast_wdt *flash_addr_wdt =
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(struct ast_wdt *)(WDT_BASE +
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sizeof(struct ast_wdt) *
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AST_FLASH_ADDR_DETECT_WDT);
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clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
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#ifndef CONFIG_FIRMWARE_2ND_BOOT
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struct ast_wdt *sec_boot_wdt =
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(struct ast_wdt *)(WDT_BASE +
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sizeof(struct ast_wdt) *
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AST_2ND_BOOT_WDT);
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clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
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#endif
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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struct udevice *dev;
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struct ram_info ram;
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int ret;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM FAIL1\r\n");
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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debug("DRAM FAIL2\r\n");
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return ret;
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}
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gd->ram_size = ram.size;
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return 0;
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}
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