mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-30 03:12:07 +00:00
1bc20897c1
Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
88 lines
2.2 KiB
Makefile
88 lines
2.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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# Copyright (C) 2017-2020 Intel Corporation <www.intel.com>
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obj-y += board.o
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obj-y += clock_manager.o
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obj-y += misc.o
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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obj-y += clock_manager_gen5.o
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obj-y += misc_gen5.o
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obj-y += reset_manager_gen5.o
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obj-y += scan_manager.o
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obj-y += system_manager_gen5.o
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obj-y += timer.o
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obj-y += wrap_pll_config.o
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obj-y += fpga_manager.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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obj-y += clock_manager_arria10.o
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obj-y += misc_arria10.o
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obj-y += pinmux_arria10.o
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obj-y += reset_manager_arria10.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
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obj-y += clock_manager_s10.o
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obj-y += lowlevel_init_soc64.o
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obj-y += mailbox_s10.o
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obj-y += misc_s10.o
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obj-y += mmu-arm64_s10.o
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obj-y += reset_manager_s10.o
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obj-y += system_manager_s10.o
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obj-y += timer_s10.o
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obj-y += wrap_pinmux_config_s10.o
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obj-y += wrap_pll_config_s10.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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obj-y += clock_manager_agilex.o
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obj-y += lowlevel_init_soc64.o
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obj-y += mailbox_s10.o
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obj-y += misc_s10.o
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obj-y += mmu-arm64_s10.o
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obj-y += reset_manager_s10.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
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obj-y += system_manager_s10.o
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obj-y += timer_s10.o
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obj-y += wrap_pinmux_config_s10.o
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obj-y += wrap_pll_config_s10.o
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endif
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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obj-y += spl_gen5.o
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obj-y += freeze_controller.o
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obj-y += wrap_iocsr_config.o
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obj-y += wrap_pinmux_config.o
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obj-y += wrap_sdram_config.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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obj-y += spl_a10.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
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obj-y += firewall.o
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obj-y += spl_s10.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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obj-y += firewall.o
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obj-y += spl_agilex.o
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endif
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else
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obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
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obj-$(CONFIG_SPL_ATF) += smc_api.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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# QTS-generated config file wrappers
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CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
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endif
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