mirror of
https://github.com/AsahiLinux/u-boot
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482 lines
9.5 KiB
C
482 lines
9.5 KiB
C
/*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <spi.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <fsl_esdhc.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_mpc83xx_serdes.h>
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#include "mpc8308.h"
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#include <gdsys_fpga.h>
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#include "../common/ioep-fpga.h"
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#include "../common/osd.h"
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#include "../common/mclink.h"
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#include "../common/phy.h"
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#include "../common/fanctrl.h"
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#include <pca953x.h>
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#include <pca9698.h>
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#include <miiphy.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MAX_MUX_CHANNELS 2
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enum {
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MCFPGA_DONE = 1 << 0,
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MCFPGA_INIT_N = 1 << 1,
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MCFPGA_PROGRAM_N = 1 << 2,
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MCFPGA_UPDATE_ENABLE_N = 1 << 3,
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MCFPGA_RESET_N = 1 << 4,
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};
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enum {
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GPIO_MDC = 1 << 14,
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GPIO_MDIO = 1 << 15,
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};
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unsigned int mclink_fpgacount;
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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struct {
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u8 bus;
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u8 addr;
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} hrcon_fans[] = CONFIG_HRCON_FANS;
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int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
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{
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int res;
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switch (fpga) {
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case 0:
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out_le16(reg, data);
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break;
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default:
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res = mclink_send(fpga - 1, regoff, data);
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if (res < 0) {
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printf("mclink_send reg %02lx data %04x returned %d\n",
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regoff, data, res);
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return res;
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}
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break;
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}
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return 0;
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}
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int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
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{
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int res;
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switch (fpga) {
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case 0:
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*data = in_le16(reg);
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break;
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default:
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if (fpga > mclink_fpgacount)
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return -EINVAL;
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res = mclink_receive(fpga - 1, regoff, data);
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if (res < 0) {
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printf("mclink_receive reg %02lx returned %d\n",
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regoff, res);
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return res;
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}
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}
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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bool hw_type_cat = pca9698_get_value(0x20, 20);
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puts("Board: ");
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printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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puts("\n");
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return 0;
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}
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int last_stage_init(void)
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{
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int slaves;
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unsigned int k;
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unsigned int mux_ch;
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unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
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u16 fpga_features;
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bool hw_type_cat = pca9698_get_value(0x20, 20);
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bool ch0_rgmii2_present = false;
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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/* Turn on Parade DP501 */
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pca9698_direction_output(0x20, 10, 1);
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pca9698_direction_output(0x20, 11, 1);
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ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
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/* wait for FPGA done, then reset FPGA */
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for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
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unsigned int ctr = 0;
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if (i2c_probe(mclink_controllers[k]))
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continue;
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while (!(pca953x_get_val(mclink_controllers[k])
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& MCFPGA_DONE)) {
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udelay(100000);
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if (ctr++ > 5) {
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printf("no done for mclink_controller %d\n", k);
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break;
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}
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}
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pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
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pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
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udelay(10);
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pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
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MCFPGA_RESET_N);
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}
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if (hw_type_cat) {
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miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
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bb_miiphy_write);
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for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
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if ((mux_ch == 1) && !ch0_rgmii2_present)
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continue;
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setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
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}
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}
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/* give slave-PLLs and Parade DP501 some time to be up and running */
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udelay(500000);
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mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
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slaves = mclink_probe();
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mclink_fpgacount = 0;
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ioep_fpga_print_info(0);
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osd_probe(0);
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#ifdef CONFIG_SYS_OSD_DH
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osd_probe(4);
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#endif
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if (slaves <= 0)
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return 0;
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mclink_fpgacount = slaves;
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for (k = 1; k <= slaves; ++k) {
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FPGA_GET_REG(k, fpga_features, &fpga_features);
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ioep_fpga_print_info(k);
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osd_probe(k);
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#ifdef CONFIG_SYS_OSD_DH
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osd_probe(k + 4);
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#endif
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if (hw_type_cat) {
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miiphy_register(bb_miiphy_buses[k].name,
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bb_miiphy_read, bb_miiphy_write);
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setup_88e1514(bb_miiphy_buses[k].name, 0);
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}
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}
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for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
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i2c_set_bus_num(hrcon_fans[k].bus);
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init_fan_controller(hrcon_fans[k].addr);
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}
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return 0;
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}
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/*
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* provide access to fpga gpios and controls (for I2C bitbang)
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* (these may look all too simple but make iocon.h much more readable)
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*/
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void fpga_gpio_set(unsigned int bus, int pin)
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{
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FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
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}
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void fpga_gpio_clear(unsigned int bus, int pin)
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{
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FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
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}
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int fpga_gpio_get(unsigned int bus, int pin)
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{
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u16 val;
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FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
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return val & pin;
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}
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void fpga_control_set(unsigned int bus, int pin)
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{
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u16 val;
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FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
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FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
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}
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void fpga_control_clear(unsigned int bus, int pin)
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{
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u16 val;
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FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
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FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
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}
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void mpc8308_init(void)
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{
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pca9698_direction_output(0x20, 4, 1);
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}
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void mpc8308_set_fpga_reset(unsigned state)
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{
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pca9698_set_value(0x20, 4, state ? 0 : 1);
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}
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void mpc8308_setup_hw(void)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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/*
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* set "startup-finished"-gpios
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*/
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setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
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setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
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}
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int mpc8308_get_fpga_done(unsigned fpga)
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{
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return pca9698_get_value(0x20, 19);
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_init(bd_t *bd)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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sysconf83xx_t *sysconf = &immr->sysconf;
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/* Enable cache snooping in eSDHC system configuration register */
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out_be32(&sysconf->sdhccr, 0x02000000);
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return fsl_esdhc_mmc_init(bd);
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}
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#endif
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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void pci_init_board(void)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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sysconf83xx_t *sysconf = &immr->sysconf;
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law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *pcie_reg[] = { pcie_regions_0 };
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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udelay(2000);
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/* Configure PCI Express Local Access Windows */
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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mpc83xx_pcie_init(1, pcie_reg);
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}
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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info->portwidth = FLASH_CFI_16BIT;
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info->chipwidth = FLASH_CFI_BY16;
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info->interface = FLASH_CFI_X16;
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return 1;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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fdt_fixup_dr_usb(blob, bd);
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fdt_fixup_esdhc(blob, bd);
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return 0;
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}
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#endif
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/*
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* FPGA MII bitbang implementation
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*/
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struct fpga_mii {
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unsigned fpga;
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int mdio;
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} fpga_mii[] = {
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{ 0, 1},
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{ 1, 1},
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{ 2, 1},
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{ 3, 1},
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};
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static int mii_dummy_init(struct bb_miiphy_bus *bus)
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{
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return 0;
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}
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static int mii_mdio_active(struct bb_miiphy_bus *bus)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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if (fpga_mii->mdio)
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
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else
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FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
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return 0;
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}
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static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
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return 0;
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}
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static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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if (v)
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
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else
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FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
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fpga_mii->mdio = v;
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return 0;
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}
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static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
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{
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u16 gpio;
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struct fpga_mii *fpga_mii = bus->priv;
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FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
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*v = ((gpio & GPIO_MDIO) != 0);
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return 0;
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}
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static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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if (v)
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
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else
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FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
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return 0;
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}
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static int mii_delay(struct bb_miiphy_bus *bus)
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{
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udelay(1);
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return 0;
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}
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struct bb_miiphy_bus bb_miiphy_buses[] = {
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{
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.name = "board0",
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.init = mii_dummy_init,
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.mdio_active = mii_mdio_active,
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.mdio_tristate = mii_mdio_tristate,
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.set_mdio = mii_set_mdio,
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.get_mdio = mii_get_mdio,
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.set_mdc = mii_set_mdc,
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.delay = mii_delay,
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.priv = &fpga_mii[0],
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},
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{
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.name = "board1",
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.init = mii_dummy_init,
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.mdio_active = mii_mdio_active,
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.mdio_tristate = mii_mdio_tristate,
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.set_mdio = mii_set_mdio,
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.get_mdio = mii_get_mdio,
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.set_mdc = mii_set_mdc,
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.delay = mii_delay,
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.priv = &fpga_mii[1],
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},
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{
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.name = "board2",
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.init = mii_dummy_init,
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.mdio_active = mii_mdio_active,
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.mdio_tristate = mii_mdio_tristate,
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.set_mdio = mii_set_mdio,
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.get_mdio = mii_get_mdio,
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.set_mdc = mii_set_mdc,
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.delay = mii_delay,
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.priv = &fpga_mii[2],
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},
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{
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.name = "board3",
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.init = mii_dummy_init,
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.mdio_active = mii_mdio_active,
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.mdio_tristate = mii_mdio_tristate,
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.set_mdio = mii_set_mdio,
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.get_mdio = mii_get_mdio,
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.set_mdc = mii_set_mdc,
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.delay = mii_delay,
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.priv = &fpga_mii[3],
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},
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};
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int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
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sizeof(bb_miiphy_buses[0]);
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