mirror of
https://github.com/AsahiLinux/u-boot
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42f8ebfd23
This adds basic BayTrail platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Note: ACPI mode support for GPIO/LPSS/SCC/LPE are not supported for now. They will be added in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
74 lines
1.2 KiB
C
74 lines
1.2 KiB
C
/*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DEVICE_H_
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#define _DEVICE_H_
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/*
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* Internal PCI device numbers within the SoC.
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*
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* Note it must start with 0x_ prefix, as the device number macro will be
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* included in the ACPI ASL files (see irq_helper.h and irq_route.h).
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*/
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/* SoC transaction router */
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#define SOC_DEV 0x00
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/* Graphics and Display */
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#define GFX_DEV 0x02
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/* MIPI */
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#define MIPI_DEV 0x03
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/* EMMC Port */
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#define EMMC_DEV 0x10
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/* SDIO Port */
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#define SDIO_DEV 0x11
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/* SD Port */
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#define SD_DEV 0x12
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/* SATA */
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#define SATA_DEV 0x13
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/* xHCI */
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#define XHCI_DEV 0x14
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/* LPE Audio */
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#define LPE_DEV 0x15
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/* OTG */
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#define OTG_DEV 0x16
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/* MMC45 Port */
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#define MMC45_DEV 0x17
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/* Serial IO 1 */
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#define SIO1_DEV 0x18
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/* Trusted Execution Engine */
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#define TXE_DEV 0x1a
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/* HD Audio */
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#define HDA_DEV 0x1b
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/* PCIe Ports */
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#define PCIE_DEV 0x1c
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/* EHCI */
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#define EHCI_DEV 0x1d
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/* Serial IO 2 */
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#define SIO2_DEV 0x1e
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/* Platform Controller Unit */
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#define PCU_DEV 0x1f
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#endif /* _DEVICE_H_ */
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