mirror of
https://github.com/AsahiLinux/u-boot
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14f643d1a2
Add Apollo Lake ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
49 lines
1.1 KiB
Text
49 lines
1.1 KiB
Text
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 Intel Corp.
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*/
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#include <asm/arch/iomap.h>
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#define MAILBOX_DATA 0x7080
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#define MAILBOX_INTF 0x7084
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#define PMIO_LENGTH 0x80
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#define PMIO_LIMIT 0x480
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scope (\_SB) {
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Device (IPC1)
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{
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Name (_HID, "INT34D2")
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Name (_CID, "INT34D2")
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Name (_DDN, "Intel(R) IPC1 Controller")
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR)
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Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT)
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Memory32Fixed (ReadWrite, 0x0, 0x4, MINF)
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IO (Decode16, IOMAP_ACPI_BASE, PMIO_LIMIT,
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0x04, PMIO_LENGTH)
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Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR)
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
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{
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PMC_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
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Store (PMC_BAR0, IBAS)
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CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
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Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA)
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CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
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Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
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CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
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Store (SRAM_BASE_0, SBAS)
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Return (^RBUF)
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}
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}
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}
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