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80b9c3bb80
The Vybrid SoC family has the same display controller unit (DCU) like the LS1021A SoC. This patch adds platform data, pinmux defines and clock control to enable the driver for Toradex Colibri Vybrid module. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
264 lines
7.9 KiB
C
264 lines
7.9 KiB
C
/*
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* Based on Linux i.MX iomux-v3.h file:
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* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
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* <armlinux@phytec.de>
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*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MACH_IOMUX_V3_H__
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#define __MACH_IOMUX_V3_H__
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#include <common.h>
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/*
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* build IOMUX_PAD structure
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*
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* This iomux scheme is based around pads, which are the physical balls
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* on the processor.
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*
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* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
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* things like driving strength and pullup/pulldown.
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* - Each pad can have but not necessarily does have an output routing register
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* (IOMUXC_SW_MUX_CTL_PAD_x).
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* - Each pad can have but not necessarily does have an input routing register
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* (IOMUXC_x_SELECT_INPUT)
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*
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* The three register sets do not have a fixed offset to each other,
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* hence we order this table by pad control registers (which all pads
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* have) and put the optional i/o routing registers into additional
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* fields.
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*
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* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
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* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
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*
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* IOMUX/PAD Bit field definitions
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*
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* MUX_CTRL_OFS: 0..11 (12)
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* PAD_CTRL_OFS: 12..23 (12)
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* SEL_INPUT_OFS: 24..35 (12)
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* MUX_MODE + SION + LPSR: 36..41 (6)
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* PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
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* SEL_INP: 60..63 (4)
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*/
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typedef u64 iomux_v3_cfg_t;
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#define MUX_CTRL_OFS_SHIFT 0
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#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
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#define MUX_PAD_CTRL_OFS_SHIFT 12
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#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
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MUX_PAD_CTRL_OFS_SHIFT)
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#define MUX_SEL_INPUT_OFS_SHIFT 24
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#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
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MUX_SEL_INPUT_OFS_SHIFT)
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#define MUX_MODE_SHIFT 36
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#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
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#define MUX_PAD_CTRL_SHIFT 42
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#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
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#define MUX_SEL_INPUT_SHIFT 60
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#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
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#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
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MUX_MODE_SHIFT)
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#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
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#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
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sel_input, pad_ctrl) \
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(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
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((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
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((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
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((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
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((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
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((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
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#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
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MUX_PAD_CTRL(pad))
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#define __NA_ 0x000
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#define NO_MUX_I 0
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#define NO_PAD_I 0
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#define NO_PAD_CTRL (1 << 17)
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#define IOMUX_CONFIG_LPSR 0x20
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#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
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MUX_MODE_SHIFT)
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#ifdef CONFIG_MX7
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#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
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#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
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#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
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#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0)
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#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0)
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#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0)
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#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0)
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#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0)
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#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0)
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#define PAD_CTL_SRE_FAST (0 << 2)
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#define PAD_CTL_SRE_SLOW (0x1 << 2)
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#define PAD_CTL_HYS (0x1 << 3)
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#define PAD_CTL_PUE (0x1 << 4)
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#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE)
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#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE)
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#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE)
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#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE)
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#else
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#ifdef CONFIG_MX6
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#define PAD_CTL_HYS (1 << 16)
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#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
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#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
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#define PAD_CTL_PKE (1 << 12)
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#define PAD_CTL_ODE (1 << 11)
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#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
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#define PAD_CTL_SPEED_LOW (0 << 6)
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#else
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#define PAD_CTL_SPEED_LOW (1 << 6)
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#endif
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#define PAD_CTL_SPEED_MED (2 << 6)
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#define PAD_CTL_SPEED_HIGH (3 << 6)
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#define PAD_CTL_DSE_DISABLE (0 << 3)
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#define PAD_CTL_DSE_240ohm (1 << 3)
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#define PAD_CTL_DSE_120ohm (2 << 3)
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#define PAD_CTL_DSE_80ohm (3 << 3)
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#define PAD_CTL_DSE_60ohm (4 << 3)
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#define PAD_CTL_DSE_48ohm (5 << 3)
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#define PAD_CTL_DSE_40ohm (6 << 3)
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#define PAD_CTL_DSE_34ohm (7 << 3)
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/* i.MX6SL/SLL */
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#define PAD_CTL_LVE (1 << 1)
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#define PAD_CTL_LVE_BIT (1 << 22)
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/* i.MX6SLL */
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#define PAD_CTL_IPD_BIT (1 << 27)
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#elif defined(CONFIG_VF610)
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#define PAD_MUX_MODE_SHIFT 20
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#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
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#define PAD_CTL_SPEED_MED (1 << 12)
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#define PAD_CTL_SPEED_HIGH (3 << 12)
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#define PAD_CTL_SRE (1 << 11)
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#define PAD_CTL_ODE (1 << 10)
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#define PAD_CTL_DSE_150ohm (1 << 6)
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#define PAD_CTL_DSE_75ohm (2 << 6)
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#define PAD_CTL_DSE_50ohm (3 << 6)
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#define PAD_CTL_DSE_37ohm (4 << 6)
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#define PAD_CTL_DSE_30ohm (5 << 6)
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#define PAD_CTL_DSE_25ohm (6 << 6)
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#define PAD_CTL_DSE_20ohm (7 << 6)
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#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PKE (1 << 3)
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#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
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#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
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#define PAD_CTL_OBE_ENABLE (1 << 1)
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#define PAD_CTL_IBE_ENABLE (1 << 0)
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#else
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#define PAD_CTL_DVS (1 << 13)
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#define PAD_CTL_INPUT_DDR (1 << 9)
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#define PAD_CTL_HYS (1 << 8)
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#define PAD_CTL_PKE (1 << 7)
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#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
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#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_ODE (1 << 3)
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#define PAD_CTL_DSE_LOW (0 << 1)
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#define PAD_CTL_DSE_MED (1 << 1)
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#define PAD_CTL_DSE_HIGH (2 << 1)
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#define PAD_CTL_DSE_MAX (3 << 1)
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#endif
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#define PAD_CTL_SRE_SLOW (0 << 0)
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#define PAD_CTL_SRE_FAST (1 << 0)
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#endif
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#define IOMUX_CONFIG_SION 0x10
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#define GPIO_PIN_MASK 0x1f
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#define GPIO_PORT_SHIFT 5
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#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
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#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
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#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
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#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
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#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
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#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
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#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
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void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
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void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
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unsigned count);
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/*
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* Set bits for general purpose registers
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*/
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void imx_iomux_set_gpr_register(int group, int start_bit,
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int num_bits, int value);
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#ifdef CONFIG_IOMUX_SHARE_CONF_REG
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void imx_iomux_gpio_set_direction(unsigned int gpio,
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unsigned int direction);
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void imx_iomux_gpio_get_function(unsigned int gpio,
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u32 *gpio_state);
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#endif
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/* macros for declaring and using pinmux array */
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#if defined(CONFIG_MX6QDL)
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#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
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#define SETUP_IOMUX_PAD(def) \
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if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \
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imx_iomux_v3_setup_pad(MX6Q_##def); \
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} else { \
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imx_iomux_v3_setup_pad(MX6DL_##def); \
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}
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#define SETUP_IOMUX_PADS(x) \
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imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
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#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
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#define IOMUX_PADS(x) MX6Q_##x
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#define SETUP_IOMUX_PAD(def) \
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imx_iomux_v3_setup_pad(MX6Q_##def);
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#define SETUP_IOMUX_PADS(x) \
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imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
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#else
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#define IOMUX_PADS(x) MX6DL_##x
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#define SETUP_IOMUX_PAD(def) \
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imx_iomux_v3_setup_pad(MX6DL_##def);
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#define SETUP_IOMUX_PADS(x) \
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imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
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#endif
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#endif /* __MACH_IOMUX_V3_H__*/
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