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af0135928e
Add the peripherals/masters definitions and registers base addresses for mx7d RDC. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
163 lines
2.7 KiB
C
163 lines
2.7 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX7D_RDC_H__
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#define __MX7D_RDC_H__
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#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */
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enum {
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RDC_PER_GPIO1 = 0,
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RDC_PER_GPIO2,
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RDC_PER_GPIO3,
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RDC_PER_GPIO4,
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RDC_PER_GPIO5,
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RDC_PER_GPIO6,
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RDC_PER_GPIO7,
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RDC_PER_IOMUXC_LPSR_GPR,
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RDC_PER_WDOG1,
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RDC_PER_WDOG2,
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RDC_PER_WDOG3,
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RDC_PER_WDOG4,
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RDC_PER_IOMUXC_LPSR,
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RDC_PER_GPT1,
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RDC_PER_GPT2,
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RDC_PER_GPT3,
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RDC_PER_GPT4,
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RDC_PER_ROMCP,
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RDC_PER_KPP,
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RDC_PER_IOMUXC,
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RDC_PER_IOMUXCGPR,
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RDC_PER_OCOTP,
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RDC_PER_ANATOP_DIG,
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RDC_PER_SNVS_HP,
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RDC_PER_CCM,
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RDC_PER_SRC,
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RDC_PER_GPC,
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RDC_PER_SEMA1,
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RDC_PER_SEMA2,
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RDC_PER_RDC,
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RDC_PER_CSU,
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RDC_PER_RESERVED1,
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RDC_PER_RESERVED2,
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RDC_PER_ADC1,
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RDC_PER_ADC2,
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RDC_PER_ECSPI4,
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RDC_PER_FLEX_TIMER1,
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RDC_PER_FLEX_TIMER2,
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RDC_PER_PWM1,
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RDC_PER_PWM2,
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RDC_PER_PWM3,
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RDC_PER_PWM4,
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RDC_PER_SYSTEM_COUNTER_READ,
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RDC_PER_SYSTEM_COUNTER_COMPARE,
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RDC_PER_SYSTEM_COUNTER_CONTROL,
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RDC_PER_PCIE_PHY,
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RDC_PER_RESERVED3,
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RDC_PER_EPDC,
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RDC_PER_PXP,
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RDC_PER_CSI,
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RDC_PER_RESERVED4,
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RDC_PER_LCDIF,
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RDC_PER_RESERVED5,
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RDC_PER_MIPI_CSI,
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RDC_PER_MIPI_DSI,
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RDC_PER_RESERVED6,
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RDC_PER_TZASC,
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RDC_PER_DDR_PHY,
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RDC_PER_DDRC,
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RDC_PER_RESERVED7,
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RDC_PER_PERFMON1,
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RDC_PER_PERFMON2,
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RDC_PER_AXI_DEBUG_MON,
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RDC_PER_QOSC,
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RDC_PER_FLEXCAN1,
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RDC_PER_FLEXCAN2,
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RDC_PER_I2C1,
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RDC_PER_I2C2,
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RDC_PER_I2C3,
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RDC_PER_I2C4,
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RDC_PER_UART4,
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RDC_PER_UART5,
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RDC_PER_UART6,
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RDC_PER_UART7,
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RDC_PER_MU_A,
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RDC_PER_MU_B,
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RDC_PER_SEMAPHORE_HS,
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RDC_PER_USB_PL301,
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RDC_PER_RESERVED8,
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RDC_PER_RESERVED9,
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RDC_PER_RESERVED10,
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RDC_PER_USB1,
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RDC_PER_USB2,
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RDC_PER_USB3,
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RDC_PER_USDHC1,
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RDC_PER_USDHC2,
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RDC_PER_USDHC3,
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RDC_PER_RESERVED11,
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RDC_PER_RESERVED12,
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RDC_PER_SIM1,
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RDC_PER_SIM2,
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RDC_PER_QSPI,
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RDC_PER_WEIM,
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RDC_PER_SDMA,
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RDC_PER_ENET1,
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RDC_PER_ENET2,
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RDC_PER_RESERVED13,
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RDC_PER_RESERVED14,
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RDC_PER_ECSPI1,
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RDC_PER_ECSPI2,
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RDC_PER_ECSPI3,
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RDC_PER_RESERVED15,
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RDC_PER_UART1,
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RDC_PER_UART2,
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RDC_PER_UART3,
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RDC_PER_RESERVED16,
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RDC_PER_SAI1,
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RDC_PER_SAI2,
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RDC_PER_SAI3,
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RDC_PER_RESERVED17,
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RDC_PER_RESERVED18,
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RDC_PER_SPBA,
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RDC_PER_DAP,
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RDC_PER_RESERVED19,
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RDC_PER_RESERVED20,
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RDC_PER_RESERVED21,
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RDC_PER_CAAM,
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RDC_PER_RESERVED22,
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};
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enum {
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RDC_MA_A7 = 0,
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RDC_MA_M4,
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RDC_MA_PCIE,
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RDC_MA_CSI,
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RDC_MA_EPDC,
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RDC_MA_LCDIF,
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RDC_MA_DISPLAY_PORT,
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RDC_MA_PXP,
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RDC_MA_CORESIGHT,
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RDC_MA_DAP,
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RDC_MA_CAAM,
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RDC_MA_SDMA_PERI,
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RDC_MA_SDMA_BURST,
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RDC_MA_APBHDMA,
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RDC_MA_RAWNAND,
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RDC_MA_USDHC1,
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RDC_MA_USDHC2,
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RDC_MA_USDHC3,
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RDC_MA_NC1,
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RDC_MA_USB,
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RDC_MA_NC2,
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RDC_MA_TEST,
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RDC_MA_ENET1_TX,
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RDC_MA_ENET1_RX,
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RDC_MA_ENET2_TX,
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RDC_MA_ENET2_RX,
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RDC_MA_SDMA,
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};
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#endif /* __MX7D_RDC_H__*/
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