mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
5b218ae106
The old mail address will stop working soon. Update it all the files Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
25 lines
951 B
C
25 lines
951 B
C
/*
|
|
* (C) Copyright 2008
|
|
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
|
|
* This work has been supported by: QTechnology http://qtec.com/
|
|
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
#ifndef XILINX_IRQ_H
|
|
#define XILINX_IRQ_H
|
|
|
|
#define intc XPAR_INTC_0_BASEADDR
|
|
#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
|
|
#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
|
|
#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
|
|
#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
|
|
#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
|
|
#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
|
|
#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
|
|
#define MER (intc + (7 * 4)) /* Master Enable Register */
|
|
|
|
#define IRQ_MASK(irq) (1 << (irq & 0x1f))
|
|
|
|
#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
|
|
|
|
#endif
|