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https://github.com/AsahiLinux/u-boot
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2b77d9a3ee
to fix following checkpatch warings. WARNING: struct should normally be const Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Exynos78x0 pinctrl driver.
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*
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* Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
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*
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* based on drivers/pinctrl/exynos/pinctrl-exynos7420.c :
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* Copyright (C) 2016 Samsung Electronics
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* Thomas Abraham <thomas.ab@samsung.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <fdtdec.h>
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#include <asm/arch/pinmux.h>
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#include "pinctrl-exynos.h"
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static const struct pinctrl_ops exynos78x0_pinctrl_ops = {
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.set_state = exynos_pinctrl_set_state
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};
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/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
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EXYNOS_PIN_BANK(6, 0x000, "etc0"),
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EXYNOS_PIN_BANK(3, 0x020, "etc1"),
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EXYNOS_PIN_BANK(8, 0x040, "gpa0"),
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EXYNOS_PIN_BANK(8, 0x060, "gpa1"),
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EXYNOS_PIN_BANK(8, 0x080, "gpa2"),
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EXYNOS_PIN_BANK(5, 0x0a0, "gpa3"),
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EXYNOS_PIN_BANK(2, 0x0c0, "gpq0"),
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};
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/* pin banks of exynos78x0 pin-controller 1 (CCORE) */
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static const struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
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EXYNOS_PIN_BANK(2, 0x000, "gpm0"),
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};
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/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */
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static const struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
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EXYNOS_PIN_BANK(4, 0x000, "gpz0"),
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EXYNOS_PIN_BANK(6, 0x020, "gpz1"),
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EXYNOS_PIN_BANK(4, 0x040, "gpz2"),
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};
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/* pin banks of exynos78x0 pin-controller 4 (FSYS) */
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static const struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
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EXYNOS_PIN_BANK(3, 0x000, "gpr0"),
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EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
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EXYNOS_PIN_BANK(2, 0x040, "gpr2"),
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EXYNOS_PIN_BANK(4, 0x060, "gpr3"),
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EXYNOS_PIN_BANK(6, 0x080, "gpr4"),
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};
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/* pin banks of exynos78x0 pin-controller 6 (TOP) */
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static const struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
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EXYNOS_PIN_BANK(4, 0x000, "gpb0"),
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EXYNOS_PIN_BANK(3, 0x020, "gpc0"),
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EXYNOS_PIN_BANK(4, 0x040, "gpc1"),
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EXYNOS_PIN_BANK(4, 0x060, "gpc4"),
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EXYNOS_PIN_BANK(2, 0x080, "gpc5"),
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EXYNOS_PIN_BANK(4, 0x0a0, "gpc6"),
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EXYNOS_PIN_BANK(2, 0x0c0, "gpc8"),
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EXYNOS_PIN_BANK(2, 0x0e0, "gpc9"),
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EXYNOS_PIN_BANK(7, 0x100, "gpd1"),
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EXYNOS_PIN_BANK(6, 0x120, "gpd2"),
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EXYNOS_PIN_BANK(8, 0x140, "gpd3"),
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EXYNOS_PIN_BANK(7, 0x160, "gpd4"),
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EXYNOS_PIN_BANK(5, 0x180, "gpd5"),
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EXYNOS_PIN_BANK(3, 0x1a0, "gpe0"),
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EXYNOS_PIN_BANK(4, 0x1c0, "gpf0"),
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EXYNOS_PIN_BANK(2, 0x1e0, "gpf1"),
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EXYNOS_PIN_BANK(2, 0x200, "gpf2"),
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EXYNOS_PIN_BANK(4, 0x220, "gpf3"),
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EXYNOS_PIN_BANK(5, 0x240, "gpf4"),
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};
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const struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
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{
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/* pin-controller instance 0 Alive data */
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.pin_banks = exynos78x0_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks0),
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}, {
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/* pin-controller instance 1 CCORE data */
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.pin_banks = exynos78x0_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks1),
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}, {
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/* pin-controller instance 2 DISPAUD data */
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.pin_banks = exynos78x0_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks2),
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}, {
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/* pin-controller instance 4 FSYS data */
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.pin_banks = exynos78x0_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks4),
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}, {
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/* pin-controller instance 6 TOP data */
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.pin_banks = exynos78x0_pin_banks6,
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.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks6),
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},
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{/* list terminator */}
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};
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static const struct udevice_id exynos78x0_pinctrl_ids[] = {
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{ .compatible = "samsung,exynos78x0-pinctrl",
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.data = (ulong)exynos78x0_pin_ctrl },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_exynos78x0) = {
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.name = "pinctrl_exynos78x0",
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.id = UCLASS_PINCTRL,
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.of_match = exynos78x0_pinctrl_ids,
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.priv_auto = sizeof(struct exynos_pinctrl_priv),
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.ops = &exynos78x0_pinctrl_ops,
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.probe = exynos_pinctrl_probe,
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};
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