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https://github.com/AsahiLinux/u-boot
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1ab557a074
SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
25 lines
491 B
ArmAsm
25 lines
491 B
ArmAsm
/*
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#define SMC_SIP_INVOKE_MCE 0x82FFFF00
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#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11)
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ENTRY(__asm_flush_l3_dcache)
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mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
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movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
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mov x1, #0
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mov x2, #0
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mov x3, #0
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mov x4, #0
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mov x5, #0
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mov x6, #0
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smc #0
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mov x0, #0
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ret
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ENDPROC(__asm_flush_l3_dcache)
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