mirror of
https://github.com/AsahiLinux/u-boot
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58d61fb5a7
J721E Starter Kit (SK)[1] is a low cost, small form factor board designed
for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high
performance vision accelerators, video codec accelerators, latest C71x
and C66x DSP, high bandwidth real-time IPs for capture and display, GPU,
dedicated safety island and security accelerators. The SoC is power
optimized to provide best in class performance for industrial and
automotive applications.
J721E SK supports the following interfaces:
* 4 GB LPDDR4 RAM
* x1 Gigabit Ethernet interface
* x1 USB 3.0 Type-C port
* x3 USB 3.0 Type-A ports
* x1 PCIe M.2 E Key
* x1 PCIe M.2 M Key
* 512 Mbit OSPI flash
* x2 CSI2 Camera interface (RPi and TI Camera connector)
* 40-pin Raspberry Pi GPIO header
Add A72 specific dts for J721E-SK.
[1] https://www.ti.com/tool/SK-TDA4VM
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
791 lines
18 KiB
Text
791 lines
18 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j721e.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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compatible = "ti,j721e-sk", "ti,j721e";
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model = "Texas Instruments J721E SK A72";
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chosen {
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stdout-path = "serial2:115200n8";
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bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
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};
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memory@80000000 {
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device_type = "memory";
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/* 4G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
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<0x00000008 0x80000000 0x00000000 0x80000000>;
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>;
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alignment = <0x1000>;
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no-map;
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};
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mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0100000 0x00 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5100000 0x00 0xf00000>;
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no-map;
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};
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c66_1_dma_memory_region: c66-dma-memory@a6000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6000000 0x00 0x100000>;
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no-map;
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};
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c66_0_memory_region: c66-memory@a6100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6100000 0x00 0xf00000>;
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no-map;
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};
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c66_0_dma_memory_region: c66-dma-memory@a7000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7000000 0x00 0x100000>;
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no-map;
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};
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c66_1_memory_region: c66-memory@a7100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7100000 0x00 0xf00000>;
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no-map;
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};
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c71_0_dma_memory_region: c71-dma-memory@a8000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa8000000 0x00 0x100000>;
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no-map;
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};
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c71_0_memory_region: c71-memory@a8100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa8100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: ipc-memories@aa000000 {
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reg = <0x00 0xaa000000 0x00 0x01c00000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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vusb_main: fixedregulator-vusb-main5v0 {
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/* USB MAIN INPUT 5V DC */
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compatible = "regulator-fixed";
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regulator-name = "vusb-main5v0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vsys_3v3: fixedregulator-vsys3v3 {
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/* Output of LM5141 */
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compatible = "regulator-fixed";
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regulator-name = "vsys_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vusb_main>;
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regulator-always-on;
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regulator-boot-on;
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};
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vdd_mmc1: fixedregulator-sd {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&vdd_mmc1_en_pins_default>;
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regulator-name = "vdd_mmc1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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enable-active-high;
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vin-supply = <&vsys_3v3>;
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gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
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};
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vdd_sd_dv_alt: gpio-regulator-tps659411 {
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compatible = "regulator-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
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regulator-name = "tps659411";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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vin-supply = <&vsys_3v3>;
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gpios = <&wkup_gpio0 9 GPIO_ACTIVE_LOW>;
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states = <3300000 0x0>,
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<1800000 0x1>;
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};
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};
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&main_pmx0 {
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main_mmc1_pins_default: main-mmc1-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
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J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
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J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
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J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
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J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
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J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
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J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
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J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
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>;
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};
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main_uart0_pins_default: main-uart0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
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J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
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J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
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J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
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>;
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};
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
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J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
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>;
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};
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main_i2c1_pins_default: main-i2c1-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
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J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
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>;
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};
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main_i2c3_pins_default: main-i2c3-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
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J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
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>;
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};
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mcu_i2c0_pins_default: mcu-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
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J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
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>;
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};
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main_usbss0_pins_default: main-usbss0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
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J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
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>;
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};
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main_usbss1_pins_default: main-usbss1-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
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>;
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};
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};
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&wkup_pmx0 {
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mcu_cpsw_pins_default: mcu-cpsw-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
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J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
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J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
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J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
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J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
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J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
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J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
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J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
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J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
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J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
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J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
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J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
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>;
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};
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mcu_mdio_pins_default: mcu-mdio1-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
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J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
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>;
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};
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mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
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J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
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J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
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J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
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J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
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J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
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J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
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J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
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J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
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J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
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J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
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>;
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};
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vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
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>;
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};
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vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
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>;
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};
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wkup_i2c0_pins_default: wkup-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
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J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
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>;
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};
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};
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&wkup_uart0 {
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/* Wakeup UART is used by System firmware */
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status = "reserved";
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};
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&main_uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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/* Shared with ATF on this platform */
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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};
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&main_uart2 {
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/* Brought out on RPi header */
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status = "disabled";
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};
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&main_uart3 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart5 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart6 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart7 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart8 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart9 {
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/* Brought out on M.2 E Key */
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status = "disabled";
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};
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&main_sdhci0 {
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/* Unused */
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status = "disabled";
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};
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&main_sdhci1 {
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/* SD Card */
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vmmc-supply = <&vdd_mmc1>;
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vqmmc-supply = <&vdd_sd_dv_alt>;
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc1_pins_default>;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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};
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&main_sdhci2 {
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/* Unused */
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status = "disabled";
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};
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&ospi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
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flash@0{
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <8>;
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spi-rx-bus-width = <8>;
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spi-max-frequency = <25000000>;
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cdns,tshsl-ns = <60>;
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cdns,tsd2d-ns = <60>;
|
|
cdns,tchsh-ns = <60>;
|
|
cdns,tslch-ns = <60>;
|
|
cdns,read-delay = <4>;
|
|
cdns,phy-mode;
|
|
cdns,phy-tx-start = <18>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
};
|
|
|
|
&ospi1 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&main_i2c0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_i2c0_pins_default>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&main_i2c1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_i2c1_pins_default>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&main_i2c3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_i2c3_pins_default>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&main_i2c4 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&main_i2c5 {
|
|
/* Brought out on RPi Header */
|
|
status = "disabled";
|
|
};
|
|
|
|
&main_i2c6 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcu_i2c0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcu_i2c0_pins_default>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&usb_serdes_mux {
|
|
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
|
|
};
|
|
|
|
&serdes_ln_ctrl {
|
|
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
|
|
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
|
|
<J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
|
|
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
|
|
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
|
|
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
|
|
};
|
|
|
|
&serdes_wiz3 {
|
|
typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
|
|
typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
|
|
};
|
|
|
|
&serdes3 {
|
|
serdes3_usb_link: link@0 {
|
|
reg = <0>;
|
|
cdns,num-lanes = <2>;
|
|
#phy-cells = <0>;
|
|
cdns,phy-type = <PHY_TYPE_USB3>;
|
|
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
|
|
};
|
|
};
|
|
|
|
&usbss0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_usbss0_pins_default>;
|
|
ti,vbus-divider;
|
|
};
|
|
|
|
&usb0 {
|
|
dr_mode = "otg";
|
|
maximum-speed = "super-speed";
|
|
phys = <&serdes3_usb_link>;
|
|
phy-names = "cdns3,usb3-phy";
|
|
};
|
|
|
|
&serdes2 {
|
|
serdes2_usb_link: link@1 {
|
|
reg = <1>;
|
|
cdns,num-lanes = <1>;
|
|
#phy-cells = <0>;
|
|
cdns,phy-type = <PHY_TYPE_USB3>;
|
|
resets = <&serdes_wiz2 2>;
|
|
};
|
|
};
|
|
|
|
&usbss1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&main_usbss1_pins_default>;
|
|
ti,vbus-divider;
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "host";
|
|
maximum-speed = "super-speed";
|
|
phys = <&serdes2_usb_link>;
|
|
phy-names = "cdns3,usb3-phy";
|
|
};
|
|
|
|
&tscadc0 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&tscadc1 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcu_cpsw {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
|
};
|
|
|
|
&davinci_mdio {
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
|
};
|
|
};
|
|
|
|
&cpsw_port1 {
|
|
phy-mode = "rgmii-rxid";
|
|
phy-handle = <&phy0>;
|
|
};
|
|
|
|
&dss {
|
|
assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
|
|
<&k3_clks 152 4>, /* VP 2 pixel clock */
|
|
<&k3_clks 152 9>, /* VP 3 pixel clock */
|
|
<&k3_clks 152 13>; /* VP 4 pixel clock */
|
|
assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
|
|
<&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */
|
|
<&k3_clks 152 11>, /* PLL18_HSDIV0 */
|
|
<&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */
|
|
};
|
|
|
|
&mcasp0 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp1 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp2 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp3 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp4 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp5 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp6 {
|
|
/* Brought out on RPi header */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp7 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp8 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp9 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp10 {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp11 {
|
|
/* Brought out on M.2 E Key */
|
|
status = "disabled";
|
|
};
|
|
|
|
&pcie2_rc {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&pcie2_ep {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&pcie3_rc {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&pcie3_ep {
|
|
/* Unused */
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster0 {
|
|
interrupts = <436>;
|
|
|
|
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
|
|
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
|
ti,mbox-rx = <2 0 0>;
|
|
ti,mbox-tx = <3 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster1 {
|
|
interrupts = <432>;
|
|
|
|
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
|
|
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
|
ti,mbox-rx = <2 0 0>;
|
|
ti,mbox-tx = <3 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster2 {
|
|
interrupts = <428>;
|
|
|
|
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
|
|
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
|
ti,mbox-rx = <2 0 0>;
|
|
ti,mbox-tx = <3 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster3 {
|
|
interrupts = <424>;
|
|
|
|
mbox_c66_0: mbox-c66-0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
|
|
mbox_c66_1: mbox-c66-1 {
|
|
ti,mbox-rx = <2 0 0>;
|
|
ti,mbox-tx = <3 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster4 {
|
|
interrupts = <420>;
|
|
|
|
mbox_c71_0: mbox-c71-0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster5 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster6 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster7 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster8 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster9 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster10 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster11 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcu_r5fss0_core0 {
|
|
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
|
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
|
<&mcu_r5fss0_core0_memory_region>;
|
|
};
|
|
|
|
&mcu_r5fss0_core1 {
|
|
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
|
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
|
<&mcu_r5fss0_core1_memory_region>;
|
|
};
|
|
|
|
&main_r5fss0_core0 {
|
|
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
|
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
|
<&main_r5fss0_core0_memory_region>;
|
|
};
|
|
|
|
&main_r5fss0_core1 {
|
|
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
|
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
|
<&main_r5fss0_core1_memory_region>;
|
|
};
|
|
|
|
&main_r5fss1_core0 {
|
|
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
|
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
|
<&main_r5fss1_core0_memory_region>;
|
|
};
|
|
|
|
&main_r5fss1_core1 {
|
|
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
|
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
|
<&main_r5fss1_core1_memory_region>;
|
|
};
|
|
|
|
&c66_0 {
|
|
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
|
memory-region = <&c66_0_dma_memory_region>,
|
|
<&c66_0_memory_region>;
|
|
};
|
|
|
|
&c66_1 {
|
|
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
|
|
memory-region = <&c66_1_dma_memory_region>,
|
|
<&c66_1_memory_region>;
|
|
};
|
|
|
|
&c71_0 {
|
|
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
|
memory-region = <&c71_0_dma_memory_region>,
|
|
<&c71_0_memory_region>;
|
|
};
|