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https://github.com/AsahiLinux/u-boot
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ef1bd8f416
if we have no NAND-Chip, we don't need the gpmc-controller and therefore is no need to init it. Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
149 lines
3.8 KiB
C
149 lines
3.8 KiB
C
/*
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* board.c
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*
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* Board functions for B&R LEIT Board
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*
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* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <power/tps65217.h>
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#include "../common/bur_common.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* --------------------------------------------------------------------------*/
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/* -- defines for GPIO -- */
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#define ETHLED_ORANGE (96+16) /* GPIO3_16 */
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#define REPSWITCH (0+20) /* GPIO0_20 */
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#if defined(CONFIG_SPL_BUILD)
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/* TODO: check ram-timing ! */
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static const struct ctrl_ioregs ddr3_ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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#ifdef CONFIG_SPL_OS_BOOT
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/*
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* called from spl_nand.c
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* return 0 for loading linux, return 1 for loading u-boot
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*/
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int spl_start_uboot(void)
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{
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if (0 == gpio_get_value(REPSWITCH)) {
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blink(5, 125, ETHLED_ORANGE);
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mdelay(1000);
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printf("SPL: entering u-boot instead kernel image.\n");
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return 1;
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}
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return 0;
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}
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#endif /* CONFIG_SPL_OS_BOOT */
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#define OSC (V_OSCK/1000000)
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static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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pmicsetup(1000);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr3;
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}
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void sdram_init(void)
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{
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config_ddr(400, &ddr3_ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SPL_BUILD */
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/* Basic board specific setup. Pinmux has been handled already. */
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_NAND
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gpmc_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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gpio_direction_output(ETHLED_ORANGE, 0);
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if (0 == gpio_get_value(REPSWITCH)) {
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printf("\n\n\n"
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"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
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"!!!!!!! recovery switch activated !!!!!!!\n"
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"!!!!!!! running usbupdate !!!!!!!\n"
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"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
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setenv("bootcmd", "sleep 2; run netupdate;");
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}
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printf("turning on display power+backlight ... ");
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tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
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0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */
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tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
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0x62, TPS65217_MASK_ALL_BITS); /* 100% */
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printf("ok.\n");
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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