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1a791892dc
LPC32xx MAC and clock control configuration requires some minor quirks to deal with a phy connected by RMII. It's worth to mention that the kernel and legacy BSP from NXP sets SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011 and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also in my tests an SMSC LAN8700 phy device connected over RMII seems to work correctly without touching this bit. Add support of RMII, if CONFIG_RMII is defined, this option is aligned with a number of boards, which already define the same config value. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
87 lines
2 KiB
C
87 lines
2 KiB
C
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/uart.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <dm.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
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static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
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void lpc32xx_uart_init(unsigned int uart_id)
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{
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if (uart_id < 1 || uart_id > 7)
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return;
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/* Disable loopback mode, if it is set by S1L bootloader */
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clrbits_le32(&ctrl->loop,
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UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
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if (uart_id < 3 || uart_id > 6)
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return;
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/* Enable UART system clock */
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setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
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/* Set UART into autoclock mode */
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clrsetbits_le32(&ctrl->clkmode,
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UART_CLKMODE_MASK(uart_id),
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UART_CLKMODE_AUTO(uart_id));
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/* Bypass pre-divider of UART clock */
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writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
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&clk->u3clk + (uart_id - 3));
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}
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void lpc32xx_mac_init(void)
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{
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/* Enable MAC interface */
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writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
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#if defined(CONFIG_RMII)
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| CLK_MAC_RMII,
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#else
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| CLK_MAC_MII,
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#endif
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&clk->macclk_ctrl);
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}
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void lpc32xx_mlc_nand_init(void)
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{
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/* Enable NAND interface */
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writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
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}
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void lpc32xx_i2c_init(unsigned int devnum)
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{
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/* Enable I2C interface */
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uint32_t ctrl = readl(&clk->i2cclk_ctrl);
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if (devnum == 1)
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ctrl |= CLK_I2C1_ENABLE;
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if (devnum == 2)
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ctrl |= CLK_I2C2_ENABLE;
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writel(ctrl, &clk->i2cclk_ctrl);
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}
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U_BOOT_DEVICE(lpc32xx_gpios) = {
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.name = "gpio_lpc32xx"
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};
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/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
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#define P_MUX_SET_SSP0 0x1600
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void lpc32xx_ssp_init(void)
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{
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/* Enable SSP0 interface */
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writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
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/* Mux SSP0 pins */
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writel(P_MUX_SET_SSP0, &mux->p_mux_set);
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}
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