mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-07 21:54:45 +00:00
7c2d5d1642
After the discussion here: https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/ which resulted in this patch: https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/ and many other discussions before it, notably: https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/ it became apparent that nobody really knows what "SGMII 2500" is. Certainly, Freescale/NXP hardware engineers name this protocol "SGMII 2500" in the reference manuals, but the PCS devices do not support any "SGMII" specific features when operating at the speed of 2500 Mbps, no in-band autoneg and no speed change via symbol replication . So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without in-band autoneg and at a fixed speed" is indistinguishable from "2500base-x without in-band autoneg", which is precisely what these NXP devices support. So it just appears that "SGMII 2500" is an unclear name with no clear definition that stuck. As such, in the Linux kernel, the drivers which use this SERDES protocol use the 2500base-x phy-mode. This patch converts U-Boot to use 2500base-x too, or at least, as much as it can. Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500 completely, but the mvpp2 driver seems to even distinguish between SGMII 2500 and 2500base-X. Namely, it enables in-band autoneg for one but not the other, and forces flow control for one but not the other. This goes back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500 is an MII protocol (connects a MAC to a PHY such as Aquantia), but the two are practically indistinguishable through everything except use case. NXP devices can support both use cases through an identical configuration, for example RX flow control can be unconditionally enabled in order to support rate adaptation performed by an Aquantia PHY. At least I can find no indication in online documents published by Cisco which would point towards "SGMII-2500" being an actual standard with an actual definition, so I cannot say "yes, NXP devices support it". Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
||
|---|---|---|
| .. | ||
| eth.c | ||
| Kconfig | ||
| ls1012ardb.c | ||
| MAINTAINERS | ||
| Makefile | ||
| README | ||
Overview
--------
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
SoC overview.
LS1012ARDB board Overview
-----------------------
- SERDES Connections, 4 lanes supporting:
- PCI Express - 3.0
- SGMII, SGMII 2.5
- SATA 3.0
- DDR Controller
- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
-QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
signals to
- QSPI NOR flash memory (2 virtual banks)
- the QSPI emulator.s
- USB 3.0
- one high-speed USB 2.0/3.0 port.
- Two enhanced secure digital host controllers:
- SDHC1 controller can be connected to onboard SDHC connector
- SDHC2 controller: Three dual 1:4 mux/demux devices,
74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
SDIO WiFi, SPI, and Ardiuno shield
- 2 I2C controllers
- One SATA onboard connectors
- UART
- The LS1012A processor consists of two UART controllers,
out of which only UART1 is used on RDB.
- ARM JTAG support
Booting Options
---------------
a) QSPI Flash Emu Boot
b) QSPI Flash 1
c) QSPI Flash 2
QSPI flash map
--------------
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
U-boot | 1MB | 0x4010_0000
U-boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
LS1012A2G5RDB board Overview
-----------------------
- SERDES Connections, 3 lanes supporting:
- SGMII, SGMII 2.5
- SATA 3.0
- DDR Controller
- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
-QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
signals to
- QSPI NOR flash memory
- USB 3.0
- one high-speed USB 2.0/3.0 port.
- SDIO WiFi, SPI
- 2 I2C controllers
- One SATA onboard connectors
- UART
- The LS1012A processor consists of two UART controllers,
out of which only UART1 is used on 2G5RDB.
- ARM JTAG support
Major Difference between LS1012ARDB and LS1012A-2G5RDB
------------------------------------------------------
1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB
2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs
of LS1012ARDB
3. LS1012A-2G5RDB is not having Arduino header
4. LS1012A-2G5RDB doesn't have PCI slot
Booting Options
---------------
QSPI Flash
QSPI flash map
--------------
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
U-boot | 1MB | 0x4010_0000
U-boot Env | 1MB | 0x4030_0000
PPA FIT image | 2MB | 0x4040_0000
PFE firmware | 20K | 0x00a0_0000
Linux ITB | ~53MB | 0x4100_0000