mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 06:04:34 +00:00
e8b68048e1
When booting from boot part1/2, the image offset should be 0, but ROM has a bug to return 0x8000. Has to workaround the issue before ROM fix it. Use a ROM function to know boot from emmc boot part or user part So we can set the image offset accordingly. Signed-off-by: Ye Li <ye.li@nxp.com>
545 lines
12 KiB
C
545 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*/
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/armv8/mmu.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/global_data.h>
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#include <efi_loader.h>
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#include <spl.h>
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#include <asm/arch/rdc.h>
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#include <asm/arch/s400_api.h>
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#include <asm/arch/mu_hal.h>
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#include <cpu_func.h>
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#include <asm/setup.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rom_api *g_rom_api = (struct rom_api *)0x1980;
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enum boot_device get_boot_device(void)
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{
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volatile gd_t *pgd = gd;
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int ret;
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u32 boot;
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u16 boot_type;
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u8 boot_instance;
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enum boot_device boot_dev = SD1_BOOT;
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ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
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((uintptr_t)&boot) ^ QUERY_BT_DEV);
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set_gd(pgd);
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if (ret != ROM_API_OKAY) {
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puts("ROMAPI: failure at query_boot_info\n");
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return -1;
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}
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boot_type = boot >> 16;
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boot_instance = (boot >> 8) & 0xff;
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switch (boot_type) {
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case BT_DEV_TYPE_SD:
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boot_dev = boot_instance + SD1_BOOT;
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break;
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case BT_DEV_TYPE_MMC:
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boot_dev = boot_instance + MMC1_BOOT;
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break;
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case BT_DEV_TYPE_NAND:
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boot_dev = NAND_BOOT;
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break;
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case BT_DEV_TYPE_FLEXSPINOR:
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boot_dev = QSPI_BOOT;
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break;
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case BT_DEV_TYPE_USB:
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boot_dev = USB_BOOT;
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break;
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default:
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break;
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}
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return boot_dev;
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}
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bool is_usb_boot(void)
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{
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return get_boot_device() == USB_BOOT;
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}
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#ifdef CONFIG_ENV_IS_IN_MMC
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__weak int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int mmc_get_env_dev(void)
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{
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volatile gd_t *pgd = gd;
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int ret;
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u32 boot;
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u16 boot_type;
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u8 boot_instance;
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ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
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((uintptr_t)&boot) ^ QUERY_BT_DEV);
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set_gd(pgd);
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if (ret != ROM_API_OKAY) {
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puts("ROMAPI: failure at query_boot_info\n");
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return CONFIG_SYS_MMC_ENV_DEV;
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}
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boot_type = boot >> 16;
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boot_instance = (boot >> 8) & 0xff;
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/* If not boot from sd/mmc, use default value */
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if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
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return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
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return board_mmc_get_env_dev(boot_instance);
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}
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#endif
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u32 get_cpu_rev(void)
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{
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return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
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}
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enum bt_mode get_boot_mode(void)
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{
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u32 bt0_cfg = 0;
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bt0_cfg = readl(SIM_SEC_BASE_ADDR + 0x24);
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bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
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if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
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/* No low power boot */
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if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
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return DUAL_BOOT;
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else
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return SINGLE_BOOT;
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}
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return LOW_POWER_BOOT;
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}
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#define CMC_SRS_TAMPER BIT(31)
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#define CMC_SRS_SECURITY BIT(30)
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#define CMC_SRS_TZWDG BIT(29)
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#define CMC_SRS_JTAG_RST BIT(28)
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#define CMC_SRS_CORE1 BIT(16)
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#define CMC_SRS_LOCKUP BIT(15)
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#define CMC_SRS_SW BIT(14)
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#define CMC_SRS_WDG BIT(13)
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#define CMC_SRS_PIN_RESET BIT(8)
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#define CMC_SRS_WARM BIT(4)
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#define CMC_SRS_HVD BIT(3)
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#define CMC_SRS_LVD BIT(2)
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#define CMC_SRS_POR BIT(1)
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#define CMC_SRS_WUP BIT(0)
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static char *get_reset_cause(char *ret)
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{
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u32 cause1, cause = 0, srs = 0;
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void __iomem *reg_ssrs = (void __iomem *)(CMC1_BASE_ADDR + 0x88);
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void __iomem *reg_srs = (void __iomem *)(CMC1_BASE_ADDR + 0x80);
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if (!ret)
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return "null";
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srs = readl(reg_srs);
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cause1 = readl(reg_ssrs);
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cause = srs & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
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switch (cause) {
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case CMC_SRS_POR:
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sprintf(ret, "%s", "POR");
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break;
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case CMC_SRS_WUP:
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sprintf(ret, "%s", "WUP");
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break;
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case CMC_SRS_WARM:
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cause = srs & (CMC_SRS_WDG | CMC_SRS_SW |
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CMC_SRS_JTAG_RST);
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switch (cause) {
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case CMC_SRS_WDG:
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sprintf(ret, "%s", "WARM-WDG");
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break;
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case CMC_SRS_SW:
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sprintf(ret, "%s", "WARM-SW");
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break;
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case CMC_SRS_JTAG_RST:
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sprintf(ret, "%s", "WARM-JTAG");
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break;
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default:
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sprintf(ret, "%s", "WARM-UNKN");
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break;
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}
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break;
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default:
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sprintf(ret, "%s-%X", "UNKN", srs);
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break;
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}
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debug("[%X] SRS[%X] %X - ", cause1, srs, srs ^ cause1);
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return ret;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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const char *get_imx_type(u32 imxtype)
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{
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return "8ULP";
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}
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int print_cpuinfo(void)
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{
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u32 cpurev;
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char cause[18];
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cpurev = get_cpu_rev();
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printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
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get_imx_type((cpurev & 0xFF000) >> 12),
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(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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printf("Reset cause: %s\n", get_reset_cause(cause));
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printf("Boot mode: ");
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switch (get_boot_mode()) {
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case LOW_POWER_BOOT:
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printf("Low power boot\n");
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break;
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case DUAL_BOOT:
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printf("Dual boot\n");
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break;
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case SINGLE_BOOT:
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default:
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printf("Single boot\n");
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break;
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}
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return 0;
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}
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#endif
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#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
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#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
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#define REFRESH_WORD0 0xA602 /* 1st refresh word */
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#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
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static void disable_wdog(void __iomem *wdog_base)
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{
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u32 val_cs = readl(wdog_base + 0x00);
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if (!(val_cs & 0x80))
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return;
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dmb();
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__raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
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__raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
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dmb();
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if (!(val_cs & 800)) {
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dmb();
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__raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
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__raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
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dmb();
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while (!(readl(wdog_base + 0x00) & 0x800))
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;
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}
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writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
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writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
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writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
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while (!(readl(wdog_base + 0x00) & 0x400))
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;
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}
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void init_wdog(void)
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{
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disable_wdog((void __iomem *)WDG3_RBASE);
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}
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static struct mm_region imx8ulp_arm64_mem_map[] = {
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{
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/* ROM */
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.virt = 0x0,
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.phys = 0x0,
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.size = 0x40000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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},
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{
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/* FLEXSPI0 */
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.virt = 0x04000000,
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.phys = 0x04000000,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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/* SSRAM (align with 2M) */
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.virt = 0x1FE00000UL,
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.phys = 0x1FE00000UL,
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.size = 0x400000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* SRAM1 (align with 2M) */
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.virt = 0x21000000UL,
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.phys = 0x21000000UL,
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.size = 0x200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* SRAM0 (align with 2M) */
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.virt = 0x22000000UL,
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.phys = 0x22000000UL,
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.size = 0x200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Peripherals */
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.virt = 0x27000000UL,
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.phys = 0x27000000UL,
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.size = 0x3000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Peripherals */
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.virt = 0x2D000000UL,
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.phys = 0x2D000000UL,
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.size = 0x1600000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* FLEXSPI1-2 */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* DRAM1 */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = PHYS_SDRAM_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/*
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* empty entrie to split table entry 5
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* if needed when TEEs are used
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*/
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0,
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = imx8ulp_arm64_mem_map;
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/* simplify the page table size to enhance boot speed */
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#define MAX_PTE_ENTRIES 512
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#define MAX_MEM_MAP_REGIONS 16
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u64 get_page_table_size(void)
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{
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u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
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u64 size = 0;
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/*
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* For each memory region, the max table size:
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* 2 level 3 tables + 2 level 2 tables + 1 level 1 table
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*/
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size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
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/*
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* We need to duplicate our page table once to have an emergency pt to
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* resort to when splitting page tables later on
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*/
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size *= 2;
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/*
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* We may need to split page tables later on if dcache settings change,
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* so reserve up to 4 (random pick) page tables for that.
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*/
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size += one_pt * 4;
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return size;
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}
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void enable_caches(void)
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{
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/* TODO: add TEE memmap region */
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icache_enable();
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dcache_enable();
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_SERIAL_TAG
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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u32 uid[4];
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u32 res;
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int ret;
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ret = ahab_read_common_fuse(1, uid, 4, &res);
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if (ret)
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printf("ahab read fuse failed %d, 0x%x\n", ret, res);
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else
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printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2], uid[3]);
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serialnr->low = uid[0];
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serialnr->high = uid[3];
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}
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#endif
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static void set_core0_reset_vector(u32 entry)
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{
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/* Update SIM1 DGO8 for reset vector base */
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writel(entry, SIM1_BASE_ADDR + 0x5c);
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/* set update bit */
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setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24);
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/* polling the ack */
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while ((readl(SIM1_BASE_ADDR + 0x8) & (0x1 << 26)) == 0)
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;
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/* clear the update */
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clrbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 24));
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/* clear the ack by set 1 */
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setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
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}
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static int trdc_set_access(void)
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{
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/*
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* TRDC mgr + 4 MBC + 2 MRC.
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* S400 should already configure when release RDC
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* A35 only map non-secure region for pbridge0 and 1, set sec_access to false
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*/
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trdc_mbc_set_access(2, 7, 0, 49, false);
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trdc_mbc_set_access(2, 7, 0, 50, false);
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trdc_mbc_set_access(2, 7, 0, 51, false);
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trdc_mbc_set_access(2, 7, 0, 52, false);
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trdc_mbc_set_access(2, 7, 0, 53, false);
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trdc_mbc_set_access(2, 7, 0, 54, false);
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/* CGC0: PBridge0 slot 47 */
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trdc_mbc_set_access(2, 7, 0, 47, false);
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/* Iomuxc0: : PBridge1 slot 33 */
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trdc_mbc_set_access(2, 7, 1, 33, false);
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return 0;
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}
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int arch_cpu_init(void)
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{
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if (IS_ENABLED(CONFIG_SPL_BUILD)) {
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/* Disable wdog */
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init_wdog();
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if (get_boot_mode() == SINGLE_BOOT) {
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release_rdc(RDC_TRDC);
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trdc_set_access();
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/* LPAV to APD */
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setbits_le32(0x2802B044, BIT(7));
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/* GPU 2D/3D to APD */
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setbits_le32(0x2802B04C, BIT(1) | BIT(2));
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/* DCNANO and MIPI_DSI to APD */
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setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4));
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}
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/* release xrdc, then allow A35 to write SRAM2 */
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release_rdc(RDC_XRDC);
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xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
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clock_init();
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} else {
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/* reconfigure core0 reset vector to ROM */
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set_core0_reset_vector(0x1000);
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}
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return 0;
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}
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int arch_cpu_init_dm(void)
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{
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struct udevice *devp;
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int node, ret;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu");
|
|
|
|
ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
|
|
if (ret) {
|
|
printf("could not get S400 mu %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_SPL_BUILD)
|
|
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
|
|
{
|
|
debug("image entry point: 0x%lx\n", spl_image->entry_point);
|
|
|
|
set_core0_reset_vector((u32)spl_image->entry_point);
|
|
|
|
/* Enable the 512KB cache */
|
|
setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4));
|
|
|
|
/* reset core */
|
|
setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 16));
|
|
|
|
while (1)
|
|
;
|
|
}
|
|
#endif
|
|
|
|
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
|
{
|
|
memset(mac, 0, 6);
|
|
}
|
|
|
|
int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;
|
|
u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
|
|
{
|
|
/* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp workaround */
|
|
if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && card_emmc_is_boot_part_en())
|
|
image_offset = 0;
|
|
|
|
return image_offset;
|
|
}
|