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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
79 lines
3 KiB
C
79 lines
3 KiB
C
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _LPC32XX_EMC_H
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#define _LPC32XX_EMC_H
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#include <asm/types.h>
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/* EMC Registers */
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struct emc_regs {
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u32 ctrl; /* Controls operation of the EMC */
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u32 status; /* Provides EMC status information */
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u32 config; /* Configures operation of the EMC */
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u32 reserved0[5];
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u32 control; /* Controls dyn memory operation */
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u32 refresh; /* Configures dyn memory refresh operation */
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u32 read_config; /* Configures the dyn memory read strategy */
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u32 reserved1;
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u32 t_rp; /* Precharge command period */
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u32 t_ras; /* Active to precharge command period */
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u32 t_srex; /* Self-refresh exit time */
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u32 reserved2[2];
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u32 t_wr; /* Write recovery time */
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u32 t_rc; /* Active to active command period */
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u32 t_rfc; /* Auto-refresh period */
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u32 t_xsr; /* Exit self-refresh to active command time */
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u32 t_rrd; /* Active bank A to active bank B latency */
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u32 t_mrd; /* Load mode register to active command time */
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u32 t_cdlr; /* Last data in to read command time */
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u32 reserved3[8];
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u32 extended_wait; /* time for static memory rd/wr transfers */
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u32 reserved4[31];
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u32 config0; /* Configuration information for the SDRAM */
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u32 rascas0; /* RAS and CAS latencies for the SDRAM */
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u32 reserved5[6];
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u32 config1; /* Configuration information for the SDRAM */
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u32 rascas1; /* RAS and CAS latencies for the SDRAM */
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u32 reserved6[54];
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struct emc_stat_t {
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u32 config; /* Static memory configuration */
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u32 waitwen; /* Delay from chip select to write enable */
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u32 waitoen; /* Delay to output enable */
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u32 waitrd; /* Delay to a read access */
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u32 waitpage; /* Delay for async page mode read */
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u32 waitwr; /* Delay to a write access */
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u32 waitturn; /* Number of bus turnaround cycles */
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u32 reserved;
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} stat[4];
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u32 reserved7[96];
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struct emc_ahb_t {
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u32 control; /* Control register for AHB */
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u32 status; /* Status register for AHB */
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u32 timeout; /* Timeout register for AHB */
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u32 reserved[5];
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} ahb[5];
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};
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/* Static Memory Configuration Register bits */
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#define EMC_STAT_CONFIG_WP (1 << 20)
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#define EMC_STAT_CONFIG_EW (1 << 8)
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#define EMC_STAT_CONFIG_PB (1 << 7)
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#define EMC_STAT_CONFIG_PC (1 << 6)
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#define EMC_STAT_CONFIG_PM (1 << 3)
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#define EMC_STAT_CONFIG_32BIT (2 << 0)
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#define EMC_STAT_CONFIG_16BIT (1 << 0)
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#define EMC_STAT_CONFIG_8BIT (0 << 0)
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/* Static Memory Delay Registers */
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#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
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#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F)
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#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
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#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
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#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
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#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)
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#endif /* _LPC32XX_EMC_H */
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